Sr High Speed Mixed Signal Circuit Design Eng

NOKIA; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Nokia in San Jose, CA is seeking a PhD/MS level analog/mixed-signal IC designer to bring high-speed ADC/DAC and PLLs to production in CMOS FinFET tech. You will design, simulate, and verify analog circuits and collaborate with layout engineers.

You will create layouts, evaluate topologies for power, area, bandwidth, and work with cross-functional teams to ensure design methodology and release flows. Required: PhD or MS in EE with 3+ years, proficiency with Cadence Virtuoso, Spectre, Calibre, and

Qualifications

• Proven track record in designing complex analog/mixed-signal IPs in deep submicron CMOS.
• Experience bringing high-speed ADCs, DACs and high-frequency low-jitter PLLs to production.
• Strong CMOS analog/mixed-signal design methodologies and circuit analysis.
• Solid understanding of device physics and layout effects.

Responsibilities

• Design, implement, and simulate high-speed analog circuits, including ADCs and DACs.
• Create layout floor plans and supervise layout engineers, hands-on if needed.
• Explore topology trade-offs to meet power/area/linearity/bandwidth requirements.
• Develop analog testing plans and characterize performance with PE/TE teams.
• Support and comply with the team's design methodologies and release flows.

Skills

Analog/mixed-signal design

CMOS deep submicron

Verilog-A/Verilog-AMS

Layout collaboration

Problem solving

Education

PhD EE

MS in EE

Tools

Cadence Virtuoso

Spectre

Incisive

Calibre

EMX

Totem EM/IR

Job description

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise

Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we've united two industry leaders to create an optical networking powerhouse-combining cutting-edge technology with proven leadership to redefine the future of connectivity.

The successful candidate shall possess the capability to design and analyze high-speed, high-performance analog/mixed-signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. She or he shall bring the design to production. Engaging in high-speed analog circuit design gives you the chance to create the technical differentiation that will allow Infinera to hold market leadership. By building cutting-edge circuitry, we will together revolutionize the era of efficient high-speed transmission.

• Design, implement, and simulate the functionality and performance of various high speed analog circuits, including the ADCs and DACs;
• Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary;
• Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc.
• Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality;
• Need to support and comply with the team's design methodologies and release flows.

Mandatory Knowledge/Skills/Abilities

• Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc.
• Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies.
• Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production.
• Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis;
• Must have a good understanding of device physics and the impacts of layout effects;
• Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS;
• Collaborative with other local or remote team members in a fast-paced professional environment.

Preferred Knowledge/Skill/Abilities

• Fluent in verbal and written communications;
• Independently resolves issues and conquer design challenges;
• Self-motivated and detail-oriented;
• Has the knowledge of (optical) communication theories and Matlab coding.

Education and Experience Requirements

• PhD EE or M.S. in E.E. with 3+ years' experience

Advancing connectivity to secure a brighter world.

Nokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we're advancing connectivity to secure a brighter world.

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Our recruitment process

We act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.

If you're interested in this role but don't meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.

The length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.