ASIC Design Engineer - ML Inference Accelerators

Amazon Web Services (AWS); Austin (TX); On-site; USD 109,700 - 160,000; Full time

Benefits offered by this job

RSUs

Sign-on payments

Comprehensive benefits

Job summary

Amazon.com Services LLC is seeking an ASIC Design Engineer in Austin, TX, to design high-performance, power-efficient RTL and collaborate with cross-functional teams across architecture, verification, and back-end implementation.

The ideal candidate has a strong background in ASIC design, SystemVerilog proficiency, and excellent analytical and problem-solving skills, with experience in high-performance and power-efficient designs.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills.
• Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing.

Responsibilities

• Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets.
• Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements.
• Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints.
• Execute lint and clock domain crossing quality checks to ensure design integrity.
• Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts.

Skills

SystemVerilog

RTL design

Clock domain crossing

Debugging

Python scripting

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree or Ph.D. in Electrical Engineering or related field

Tools

Python

Perl

Job description

Amazon.com Services LLC is seeking an ASIC Design Engineer in Austin, TX, to design high-performance, power-efficient RTL and collaborate with cross-functional teams across architecture, verification, and back-end implementation.

The ideal candidate has a strong background in ASIC design, SystemVerilog proficiency, and excellent analytical and problem-solving skills, with experience in high-performance and power-efficient designs.