Chiplet Performance & Power Architect — Remote-Friendly

TYLsemi; San Jose (CA); Hybrid; USD 204,000 - 250,000; Full time

Job summary

TYLsemi is seeking a Lead Performance Architect to drive architectural configuration, system-level simulation, and PPA optimization of the chiplet using industry-standard ESL tools or in-house solutions.

You will own the trade-off analyses that define tape-out decisions, build transaction-level models with ESL suites, sweep hardware parameters, and collaborate with IP vendors to integrate PCIe, UCIe and NoC into a full-chiplet model.

Qualifications

• BS/MS in Electrical Engineering or related field with 6+ years in computer architecture, performance modeling, or microarchitecture configuration.
• Hands-on experience with ESL tools such as Platform Architect, Virtualizer, or comparable frameworks.
• Strong knowledge of PCIe (Gen 5/6/7), UCIe, or AMBA NoC protocols and willingness to learn others.

Responsibilities

• Own PPA exploration and trade-offs between peak performance, silicon area, and thermal/power budgets, and turn that into clear tape-out recommendations.
• Build transaction-level models (TLM) using ESL suites that integrate PCIe, UCIe, and NoC into a full-chiplet model.
• Define, sweep, and validate hardware configuration parameters to maximize throughput and minimize latency across realistic workloads.
• Characterize traffic across the internal NoC and UCIe die-to-die interface to find congestion points and rule out protocol deadlocks.
• Work with IP vendors to debug model/behavioral mismatches and integrate new IP deliverables as they land.

Skills

Python

SystemC

Performance modeling

PCIe/UCIe/NoC protocols

Traffic generators

Education

BS/MS in Electrical Engineering or related field

Tools

Platform Architect

Virtualizer

Custom ESL tools

Job description

TYLsemi is seeking a Lead Performance Architect to drive architectural configuration, system-level simulation, and PPA optimization of the chiplet using industry-standard ESL tools or in-house solutions.

You will own the trade-off analyses that define tape-out decisions, build transaction-level models with ESL suites, sweep hardware parameters, and collaborate with IP vendors to integrate PCIe, UCIe and NoC into a full-chiplet model.