Lead SoC Performance Architect, AI Compute

Arm Limited; Austin (TX); Hybrid; USD 309,000 - 418,000; Full time

Job summary

Arm Limited is seeking an experienced system performance architect to drive performance exploration and define use-case requirements for future compute infrastructure across data center and networking domains.

You will work in small teams to translate roadmaps into performant systems, collaborating with modeling, RTL, FPGA, silicon, and software groups to push the limits of system performance, power, and area optimization.

Qualifications

• At least 10 years SoC system performance experience using models, RTL simulation, emulation or FPGA.
• Deep knowledge of infrastructure system architecture and performance including multi-die coherent memory systems and PCIe.
• Passion for analysis and improvement including performance, power, area optimization.
• Capable of working both in teams and independently.
• High degree of initiative and a confident problem solver.
• Excellent communicator, able to work and communicate at both a detailed and high level.

Responsibilities

• Define SoC system and subsystem use-case performance and analysis requirements.
• Drive the analysis and testing of performance from models to RTL.
• Partner with system architects, IP and technology teams to translate vision and roadmaps into achieved performant systems.
• Engage with specialists across Arm, from modeling, RTL, FPGA, Silicon and software.
• Explore and challenge the limits of system and IP performance capabilities.

Skills

System performance analysis

RTL/FPGA experience

Independent work

Communication skills

Team collaboration

Arm architecture familiarity

Education

University degree (or PhD) in Electronic Engineering / CS / Math / Data Analytics or related field

Tools

RTL simulation

FPGA

Emulation

Job description

Arm Limited is seeking an experienced system performance architect to drive performance exploration and define use-case requirements for future compute infrastructure across data center and networking domains.

You will work in small teams to translate roadmaps into performant systems, collaborating with modeling, RTL, FPGA, silicon, and software groups to push the limits of system performance, power, and area optimization.