Chip Package SI/PI Engineer for AI/ML Accelerators

Google; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google Sunnyvale is hiring a Chip Package SI/PI Engineer to advance TPU hardware acceleration. You will verify complex digital designs, focusing on TPU architecture and AI/ML system integration, shaping next‑gen silicon solutions used by millions of users.

As part of the chip implementation team you’ll drive packaging SI/PI across cross‑functional groups, collaborate with design, packaging, system teams and vendors, and help deliver production‑readiness for high‑speed interconnects.

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CE/CS.
• 10 years of experience with SI/PI design for chip/package or system PCB.
• Experience with industry SIPI modeling tool chains (HFSS, ADS, Sigrity, Siwave, etc.).
• Master’s or PhD in EE or SI/PI is preferred for advanced roles.

Responsibilities

• Drive chip-package-system co-design by performing SI/PI analysis and optimization for HPC based on 2.5D/3D package technology.
• Develop Power integrity methodology for advanced package technology and improve accuracy and productivity.
• Evaluate new package technology and high-speed interface IP.
• Collaborate with chip design, system design and supplier teams to meet design targets and tradeoffs for production.
• Provide feedback on chip floorplan considering package/system routability and SI/PI.

Skills

SI/PI design experience

Chip/package or system PCB experience

Automation using Python/ Matlab/ C++

Education

Bachelor's degree in EE/CE/CS or related

Master’s or PhD in EE or SI/PI (preferred)

Tools

HFSS

ADS

Sigrity

Siwave

Job description

Google Sunnyvale is hiring a Chip Package SI/PI Engineer to advance TPU hardware acceleration. You will verify complex digital designs, focusing on TPU architecture and AI/ML system integration, shaping next‑gen silicon solutions used by millions of users.

As part of the chip implementation team you’ll drive packaging SI/PI across cross‑functional groups, collaborate with design, packaging, system teams and vendors, and help deliver production‑readiness for high‑speed interconnects.