Principal Physical Design Engineer — Lead High-Perf Chips

Delos Data; Palo Alto (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Delos Data is seeking a Principal Physical Design Engineer to join as an early member of the team in Silicon Valley. You will own complex physical implementations from floorplan through signoff, driving timing closure, power integrity, and robust PPA improvements.

You will lead cross-functional collaboration with RTL, architecture, and packaging teams, shaping methodologies and flows for high-performance AI data center work.

Qualifications

• 10+ years ASIC/SoC physical design experience with multiple tapeouts.
• Expert-level floorplanning, placement, CTS, routing, timing closure, ECOs, and physical verification.
• Strong knowledge of static timing analysis and multi-mode/multi-corner timing.

Responsibilities

• Own physical implementation of complex blocks and subsystems through signoff.
• Develop floorplans with hierarchy, macros, interfaces, congestion, timing, power and routability.
• Drive power-grid implementations, IR-drop, and electromigration closure.
• Lead placement, clock-tree synthesis, routing, extraction, timing closure, and ECO.
• Resolve setup/hold, signal integrity, congestion, and physical implementation issues.
• Coordinate with RTL and architecture teams to fix problems early.
• Improve physical design flows, scripts, automation, metrics, and methodologies.

Skills

Floorplanning

Placement

CTS

Routing

Timing closure

Physical verification

Static timing analysis

Power delivery

IR drop

Electromigration

Clock design

Extraction

Scripting (Tcl, Python, Perl)

Debug RTL/Timing/Signoff

Technical leadership

Tools

Cadence

Synopsys

Job description

Delos Data is seeking a Principal Physical Design Engineer to join as an early member of the team in Silicon Valley. You will own complex physical implementations from floorplan through signoff, driving timing closure, power integrity, and robust PPA improvements.

You will lead cross-functional collaboration with RTL, architecture, and packaging teams, shaping methodologies and flows for high-performance AI data center work.