Senior Digital Design Engineer — RTL & AI-Enabled

Micron Technology, Inc

Richardson (TX)

On-site

USD 120,000 - 180,000

Full time

12 days ago

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Benefits offered by this job

Medical plan
Dental plan
Vision plan
Paid time off
Paid holidays
Wellbeing programs

Job summary

Micron Technology, Inc. in Richardson, TX seeks a Senior Digital Design Engineer for HBM to drive the full digital design flow from concept to post-silicon debug, delivering high‑quality RTL in Verilog/SystemVerilog.

You will refine micro-architecture, trade off area/power/latency, and collaborate with verification, DFT, physical design and CAD teams to ensure robust design closure and testability.

Responsibilities

  • Drive all stages of the digital design flow, from concept to post-silicon debug.
  • Develop high-quality RTL in Verilog/SystemVerilog using scalable design techniques.
  • Define and refine micro-architecture for digital logic blocks including FSMs, datapaths, FIFOs, pipelines and arbitration.
  • Analyze tradeoffs across area, power, latency, and throughput with clear documentation of design decisions.
  • Utilize AI-enabled tools to assist with daily execution.
  • Perform CDC/RDC analysis, apply clocking and reset strategies, and identify timing challenges.
  • Support synthesis and static timing analysis by creating and debugging SDC constraints and timing reports.
  • Apply low-power design methodologies including CPF/UPF, clock gating, and multi‑domain partitioning.
  • Collaborate with verification, DFT, physical design and CAD teams to ensure robust closure and high coverage.
  • Ensure scan/ATPG readiness and support formal verification.

Job description

Micron Technology, Inc. in Richardson, TX seeks a Senior Digital Design Engineer for HBM to drive the full digital design flow from concept to post-silicon debug, delivering high‑quality RTL in Verilog/SystemVerilog.

You will refine micro-architecture, trade off area/power/latency, and collaborate with verification, DFT, physical design and CAD teams to ensure robust design closure and testability.

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