Chief Memory Architect & Engineer — End-to-End IC Design

WD; San Jose (CA); Vor Ort; USD 243.000 - 324.000; Vollzeit

Zusammenfassung

WD is seeking the most senior technical individual contributor in memory design to own end-to-end product architecture from concept through silicon qualification. You will arbitrate power/performance/area trade-offs and serve as the final technical authority across design, process and product engineering.

Responsibilities include defining the memory subsystem architecture, driving floorplan and physical architecture, owning multi-generation roadmaps, and guiding cross-functional trade-offs and

Qualifikationen

• MS/PhD in EE, CE or related field.
• 15+ years in memory or mixed-signal IC development; 5+ as architect or chief engineer.
• 2+ memory products owned from architecture through production silicon.
• Deep CMOS FinFET expertise: layout, variability, reliability, DFM.
• Memory architecture breadth (DRAM, NAND/NOR, SRAM, emerging NVM).
• Cadence/Synopsys custom and digital flows through full-chip sign-off.
• Owned EDA/CAD strategy; led multi-site programs through influence.

Aufgaben

• Define memory subsystem architecture and translate requirements into design specs.
• Drive floorplan and physical architecture including power delivery and SI.
• Own multi-generation roadmap: node migration and density/performance scaling.
• Decide cross-functional trade-offs across process, circuits, DFT, packaging and interfaces.
• Oversee design methodology and EDA/CAD strategy (tools, vendors, licenses).
• Mentor engineers through architecture and design reviews.
• Represent architecture to executives, customers, foundry partners and standards bodies.

Kenntnisse

Memory architecture breadth

CMOS FinFET expertise

EDA/CAD strategy

Cross-functional leadership

Architecture and design reviews

Ausbildung

MS/PhD in EE or CE

Tools

Cadence/Synopsys flows

Jobbeschreibung

WD is seeking the most senior technical individual contributor in memory design to own end-to-end product architecture from concept through silicon qualification. You will arbitrate power/performance/area trade-offs and serve as the final technical authority across design, process and product engineering.

Responsibilities include defining the memory subsystem architecture, driving floorplan and physical architecture, owning multi-generation roadmaps, and guiding cross-functional trade-offs and