Cache Coherence Architect, NoC IP Leader (Equity)

NVIDIA Corporation; United States; In loco; USD 152.000 - 288.000; Tempo pieno

Vantaggi offerti da questo lavoro

Equity

Benefits

Descrizione del lavoro

NVIDIA Corporation seeks an experienced Senior Cache Coherency Architect to join our team, developing scalable, low-latency, high-bandwidth coherent interconnect systems powering Grace products and beyond.

You will define interconnect architectures, collaborate with CPU/GPU/memory/SoC architects, model and implement cache-coherent subsystems, and support silicon bring-up. Eligible for equity and benefits; applications accepted until November 3, 2026.

Competenze

• Master's degree required in electrical/computer engineering or computer science.
• 5+ years of experience in processor design or high-performance semiconductor designs.
• Deep understanding of cache coherency with hands-on experience in AXI/ACE/CHI.
• Experience authoring specifications and designing cache-coherent interconnects.
• Strong understanding of system and memory subsystem architecture with cache-coherent interconnect.

Mansioni

• Define consistent interconnect architecture and cache-coherency protocols.
• Contribute to interconnect IP block specs, build, verification, and integration into NoC fabric.
• Collaborate with architects to align interconnects with PPA requirements.
• Develop and maintain functional and performance models for NoC fabric and IP units.
• Work with design/verification teams (simulation, emulation, formal) to match architecture specs.
• Support silicon bring-up and post-silicon debug as needed.

Conoscenze

C

C++

Python

Verilog

Cache coherency

NoC

Formazione

Master's degree in EE/CE/CS

Strumenti

VIPs

BFMs

Descrizione del lavoro

NVIDIA Corporation seeks an experienced Senior Cache Coherency Architect to join our team, developing scalable, low-latency, high-bandwidth coherent interconnect systems powering Grace products and beyond.

You will define interconnect architectures, collaborate with CPU/GPU/memory/SoC architects, model and implement cache-coherent subsystems, and support silicon bring-up. Eligible for equity and benefits; applications accepted until November 3, 2026.