Brain-Interface SoC Co-Design Engineer (DSP/AI)

Roboticsconnected; Austin (TX); On-site; USD 151,000 - 261,000; Full time

Benefits offered by this job

Equity (RSUs)

401(k) plan

Medical insurance

Dental insurance

Vision insurance

Paid holidays

Commuter benefits

Meals provided

Parental leave

Flexible time off

Job summary

Neuralink is seeking a Hardware/Software Co-Design Engineer to deliver micro-architecture and RTL for high-throughput, low-power DSPs and accelerators in brain-machine interfaces. You will work with firmware teams to optimize hardware/software interfaces and drive architecture trade-offs across process technology and workload types.

The role requires strong SystemVerilog, C/C++, Python skills, and a track record in RTL design, emulation, and DSP pipelines from algorithm to implementation.

Qualifications

• Bachelor degree or equivalent experience in electrical engineering, computer science, or related field.
• Evidence of exceptional ability in EE/CS/CE.
• Experience designing embedded software in C or Rust.
• Expertise in SystemVerilog, C/C++, Python.
• Experience emulation models, transactors, and test environments for hardware behavior.
• Experience in complex digital systems from architecture to RTL.
• Experience designing DSP pipelines from algorithm to RTL.

Responsibilities

• Deliver micro-architecture and RTL implementations of low-power DSPs, accelerators, GPUs, and PHY/MAC for brain-machine interfaces.
• Design and optimize hardware/software interface with firmware engineers.
• Perform architecture optimization balancing energy, performance, and cost under process variation.
• Collaborate on silicon bring-up tests with verification teams.

Skills

SystemVerilog

C/C++

Python

Rust

Education

B.S. in Electrical Engineering / Computer Science

Job description

Neuralink is seeking a Hardware/Software Co-Design Engineer to deliver micro-architecture and RTL for high-throughput, low-power DSPs and accelerators in brain-machine interfaces. You will work with firmware teams to optimize hardware/software interfaces and drive architecture trade-offs across process technology and workload types.

The role requires strong SystemVerilog, C/C++, Python skills, and a track record in RTL design, emulation, and DSP pipelines from algorithm to implementation.