Digital IC Design Intern for Next-Gen Brain Interfaces

Neuralink; South San Francisco (CA); On-site; USD 39,778 - 56,653; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Meal provided

RSUs

401(k)

Paid holidays

Parental leave

Flexible time off

Job summary

Neuralink in California is seeking a Digital IC Design Engineer Intern to contribute to micro-architecture design and RTL implementation of low-power accelerators and SoC components for next-generation brain-computer interfaces.

You will collaborate with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team, tackling energy efficiency, performance, and verification challenges on silicon bring-up.

Qualifications

• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering.
• 2+ years of experience in digital design.
• Proficient in SystemVerilog, C/C++, Python.
• Experience in designing digital signal processing pipelines, from algorithm to RTL.

Responsibilities

• Micro-architecture design and RTL implementation of low-power general-purpose hardware accelerators.
• Low-power GPUs and serial link MAC/PHY designs.
• Interface hardware/software with firmware engineers.
• Architecture optimization balancing energy, performance, and process variation.
• Collaborate with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team.

Skills

SystemVerilog

C/C++

Python

RTL design

Tools

EDA tools

Job description

Neuralink in California is seeking a Digital IC Design Engineer Intern to contribute to micro-architecture design and RTL implementation of low-power accelerators and SoC components for next-generation brain-computer interfaces.

You will collaborate with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team, tackling energy efficiency, performance, and verification challenges on silicon bring-up.