Low-Power Digital IC Design Engineer Intern

NeuroTechX; South San Francisco (CA); In loco; USD 41.000 - 55.000; Tempo pieno

Vantaggi offerti da questo lavoro

Excellent medical, dental, and vision

Paid holidays

Commuter benefits

Meals provided

Equity (RSUs)

401(k) plan

Parental leave

Flexible time off

Descrizione del lavoro

Neuralink seeks experienced engineers for a Digital IC Design Engineer Intern role focused on next-generation chip architectures and hardware accelerators. You will collaborate with chip designers, electrical engineers, algorithms engineers, and software engineers on a compact, agile team to push the boundaries of energy efficiency and silicon technology.

The position emphasizes hands-on RTL, micro-architecture, and verification work, with opportunities to influence silicon bring-up and test

Competenze

• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• 2+ years of experience in digital design
• Proficient in SystemVerilog, C/C++, Python
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Mansioni

• Micro-architecture design and RTL implementation of low-power DSPs, accelerators, GPUs, and radio MAC/PHY
• Design and implementation of hardware/software interface with firmware engineers
• Architecture optimization including energy efficiency and performance with process technology
• Complex system-on-chip verification: behavioral modeling, verification, and FPGA emulation
• Collaboration on silicon bring-up tests with validation engineers

Conoscenze

Electrical engineering

Computer science

Computer engineering

SystemVerilog

C/C++

Python

RTL design

Digital design

Descrizione del lavoro

Neuralink seeks experienced engineers for a Digital IC Design Engineer Intern role focused on next-generation chip architectures and hardware accelerators. You will collaborate with chip designers, electrical engineers, algorithms engineers, and software engineers on a compact, agile team to push the boundaries of energy efficiency and silicon technology.

The position emphasizes hands-on RTL, micro-architecture, and verification work, with opportunities to influence silicon bring-up and test