Brain-Interface SoC Verification Engineer | Equity RSUs

Neuralink; San Francisco (CA); On-site; USD 131,000 - 243,000; Full time

Benefits offered by this job

Equity (RSUs)

401(k) plan

Paid holidays

Meals provided

Flexible time off

Job summary

Neuralink is seeking an ASIC Design Verification Engineer to join the SoC team in the Implant Group. You will work on high‑throughput, low‑power DSP‑focused digital modules, building robust verification environments and test benches for brain‑computer interface hardware.

The role requires strong SystemVerilog skills and hands‑on experience with verification methodologies, UVM, and script automation. Base salary includes RSU equity for full‑time staff at Neuralink in San Francisco.

Qualifications

• Minimum 3 years of experience in digital ASIC verification.
• Excellence in SystemVerilog.
• Experience with automation flow and scripts (Python, Perl, Makefile, Tcl, UNIX shell).
• Experience with code coverage and regression setup.

Responsibilities

• Verify digital ASIC designs for correctness and performance.
• Develop and maintain automation flows and test scripts.
• Build and debug test benches for complex SoC systems.
• Collaborate on verification methodologies including UVM and formal techniques.

Skills

ASIC verification

SystemVerilog

Automation scripting

Job description

Neuralink is seeking an ASIC Design Verification Engineer to join the SoC team in the Implant Group. You will work on high‑throughput, low‑power DSP‑focused digital modules, building robust verification environments and test benches for brain‑computer interface hardware.

The role requires strong SystemVerilog skills and hands‑on experience with verification methodologies, UVM, and script automation. Base salary includes RSU equity for full‑time staff at Neuralink in San Francisco.