Back-End Process Integration Engineer — Yield & RC Optimization

Intel; Hillsboro (OR); On-site; USD 104,000 - 171,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Vacation

Job summary

Intel in United States (Oregon, Hillsboro) seeks a PhD-level engineer to develop integrated process flows for new technology nodes and coordinate interdisciplinary teams across lithography, etch, deposition, diffusion, and metrology. The role emphasizes RC optimization, process window establishment, and reliability analysis.

The candidate will perform root-cause analysis using SPC/DOE/FMEA, drive corrective actions, document SOPs, and support ramp from R&D to high-volume manufacturing.

Qualifications

• PhD in Electrical Engineering, Physics, Applied Physics, Materials Science, Chemical Engineering, Mechanical Engineering, Chemistry, Optics, or a closely related semiconductor field of study.

Responsibilities

• Develop and define integrated front-end and back-end process flows for new technology nodes.
• Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, dielectric, and metrology teams.
• Optimize RC (resistance-capacitance) performance.
• Establish process windows and integration schemes.
• Analyze yield loss and parametric failures.
• Perform root cause analysis using statistical tools (SPC, DOE, FMEA).
• Drive corrective actions to improve yield and cycle time.
• Implement control plans and process monitoring strategies.
• Use statistical tools such as: Cpk / Ppk, Control charts, Capability analysis
• Ensure margins for electromigration, stress migration, TDDB, time dependent via degradation.
• Evaluate impact of process window shifts on reliability.
• Support ramp from R and D to high-volume manufacturing (HVM).
• Document process specifications and standard operating procedures (SOPs).

Skills

RC delay expertise

TDDB

Stats & data analysis

Presentation skills

Cross-disciplinary influence

Education

PhD in Electrical Engineering or related

Tools

JMP

Python

SQL

MATLAB

JSL

TCL

Job description

Intel in United States (Oregon, Hillsboro) seeks a PhD-level engineer to develop integrated process flows for new technology nodes and coordinate interdisciplinary teams across lithography, etch, deposition, diffusion, and metrology. The role emphasizes RC optimization, process window establishment, and reliability analysis.

The candidate will perform root-cause analysis using SPC/DOE/FMEA, drive corrective actions, document SOPs, and support ramp from R&D to high-volume manufacturing.