Avionics ASIC/FPGA Verification Engineer (UVM)

Lockheed Martin; Denver (CO); On-site; USD 136,000 - 252,000; Full time

Benefits offered by this job

Medical

Dental

Vision

Flexible work arrangements (4x10)

401(k) match

Paid time off

Holidays

Parental Leave

EAP

Flexible Spending Accounts

Education Assistance

Life Insurance

Short-Term Disability

Long-Term Disability

Job summary

Lockheed Martin is seeking an ASIC/FPGA Verification Engineer to contribute to the development of state-of-the-art avionics products. The role requires hands-on verification across FPGA/ASIC domains using UVM/OVM/VMM and HDL languages.

On-site office location in Denver/Highlands Ranch and Sunnyvale, CA is required. You will work a 9x80 schedule, in-office, with opportunities to engage in design, verification, and documentation of complex silicon.

Qualifications

• Bachelor of Science or higher in Electrical Engineering or related discipline, or equivalent experience/combined education.
• Experience in the verification of FPGA and/or ASIC devices.
• Experience with modern verification methodologies such as UVM, OVM or VMM.
• HDL programming experience with VHDL, Verilog, and/or SystemVerilog.

Responsibilities

• Develops, designs, verifies, and documents ASIC/FPGA development from high-level design to synthesis, place and route, and timing analysis.
• Performs system-level verification and power utilization assessments.
• Utilizes specialized equipment to establish operation data and evaluate test results.

Skills

FPGA/ASIC verification

UVM/OVM/VMM

HDL languages (VHDL/Verilog/SystemVeri

Lab testing

Python scripting

Education

Bachelor of Science in Electrical Engineering or related

Tools

MS Project

JIRA

Job description

Lockheed Martin is seeking an ASIC/FPGA Verification Engineer to contribute to the development of state-of-the-art avionics products. The role requires hands-on verification across FPGA/ASIC domains using UVM/OVM/VMM and HDL languages.

On-site office location in Denver/Highlands Ranch and Sunnyvale, CA is required. You will work a 9x80 schedule, in-office, with opportunities to engage in design, verification, and documentation of complex silicon.