Senior ASIC/FPGA Verification Engineer (Contract, UVM)

Boeing; El Segundo (CA); On-site; USD 145,000 - 152,000; Full time

Benefits offered by this job

Medical benefits

Dental benefits

Vision benefits

401K

Job summary

Boeing is seeking a contract verification engineer for a non-managerial project assignment conducted through a Boeing approved third party. Regular and predictable attendance is required.

You will resolve complex issues on critical programs, lead the technical aspects of proposal preparation, and coordinate engineering support through the product lifecycle, while developing new concepts for future designs. Required: 7+ years in verification with UVM, strong SystemVerilog/UVM, self‑checking,

Qualifications

• 7+ years of verification experience with UVM (2+ UVM experience acceptable if solid).
• Strong SystemVerilog and UVM experience.
• Self-checking and constrained-random verification; verification planning.
• Debugging; coverage closure.
• Active U.S. security clearance.

Responsibilities

• Resolves complex issues on critical programs related to architectural approaches, requirements, specifications and design.
• Leads technical aspect of proposal preparation.
• Coordinates engineering support throughout the lifecycle of the product.
• Develops new concepts for future product designs to meet projected requirements.
• Recommends and manages technology insertion.
• Works under consultative direction.

Skills

Verification engineering

UVM experience

SystemVerilog

Constrained-random verification

Debugging

Security clearance

Job description

Boeing is seeking a contract verification engineer for a non-managerial project assignment conducted through a Boeing approved third party. Regular and predictable attendance is required.

You will resolve complex issues on critical programs, lead the technical aspects of proposal preparation, and coordinate engineering support through the product lifecycle, while developing new concepts for future designs. Required: 7+ years in verification with UVM, strong SystemVerilog/UVM, self‑checking,