ASIC Verification Engineer – SystemVerilog & UVM

Blue Origin; Van Horn (TX); On-site; USD 129,000 - 181,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Life insurance

Parental leave

Disability insurance

401(k)

Stock options

Paid time off

Holidays

Job summary

Blue Origin is seeking engineers to contribute to Verilog/SystemVerilog design and verification of digital blocks for SoCs. You will support module-level verification using UVM, write test plans, and assist with coverage metrics under guidance from senior team members.

Responsibilities include debugging RTL/testbenches, integrating IP, and applying verification methodologies like UVM and formal verification basics to ensure safe, repeatable spaceflight hardware.

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or related technical field (completed or in final year).
• Coursework or project experience with Verilog/SystemVerilog RTL design or verification.
• Understanding of digital logic design fundamentals (combinational/sequential logic, FSMs, timing).
• Familiarity with basic verification concepts (testbenches, simulation, coverage).
• Strong problem-solving skills and attention to detail.
• Effective communication and ability to work in a collaborative team environment.

Responsibilities

• Contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs
• Support module-level and subsystem-level verification using SystemVerilog/UVM
• Write test plans and functional coverage definitions under guidance from senior team members
• Assist with CDC/RDC/LINT checks and clean-up
• Participate in code coverage and functional coverage closure activities
• Help develop assertions, protocol monitors, and scoreboards for testbenches
• Support integration and verification of external IP (e.g., bus fabrics, standard interfaces)
• Learn and apply industry-standard verification methodologies (UVM, formal verification basics)
• Debug RTL and testbench issues with guidance from senior engineers
• Document design intent, verification results, and test coverage

Skills

Verilog/SystemVerilog RTL design

SystemVerilog verification

UVM

Digital logic fundamentals

Testbenches

Communication skills

Education

BS or MS in Electrical Engineering or related

Tools

VCS/Xcelium/Questa

Job description

Blue Origin is seeking engineers to contribute to Verilog/SystemVerilog design and verification of digital blocks for SoCs. You will support module-level verification using UVM, write test plans, and assist with coverage metrics under guidance from senior team members.

Responsibilities include debugging RTL/testbenches, integrating IP, and applying verification methodologies like UVM and formal verification basics to ensure safe, repeatable spaceflight hardware.