ASIC Verification Engineer — Verilog/SystemVerilog

Blue Origin; Seattle (WA); On-site; USD 129,000 - 181,000; Full time

Benefits offered by this job

Medical Insurance

401(k) with company match

Paid Time Off

Education Support Program

Stock Options

Job summary

Blue Origin LLC is seeking early-to-mid career engineers to contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs. You will write test plans, define functional coverage, and assist with CDC/RDC/LINT checks under guidance from senior team members.

Join a collaborative, safety-focused culture and help advance verification methodologies (UVM, formal) across active hardware projects.

Qualifications

• BS or MS in Electrical/Computer Engineering or related field.
• Experience with Verilog/SystemVerilog RTL design or verification.
• Understanding of digital logic, FSMs, timing.
• Familiarity with verification concepts (testbenches, coverage).
• Strong problem-solving and attention to detail.

Responsibilities

• Contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs.
• Write test plans and functional coverage definitions.
• Assist with CDC/RDC/LINT checks and clean-up.
• Debug RTL and testbench issues with guidance from senior engineers.
• Document design intent, verification results, and test coverage.

Skills

Verilog/SystemVerilog

UVM verification

Digital logic

Testbench debugging

Team communication

Education

BS/MS in Electrical or Computer Engineering

Tools

VCS

Xcelium

Questa

Formal tools

Python scripting

Job description

Blue Origin LLC is seeking early-to-mid career engineers to contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs. You will write test plans, define functional coverage, and assist with CDC/RDC/LINT checks under guidance from senior team members.

Join a collaborative, safety-focused culture and help advance verification methodologies (UVM, formal) across active hardware projects.