Lead ASIC Verification Engineer — UVM & SystemVerilog

Blue Origin; Los Angeles (CA); On-site; USD 197,529 - 276,539; Full time

Benefits offered by this job

Medical, dental, and vision insurance

401(k) with company match

Paid parental leave

Stock options

Job summary

Blue Origin in Los Angeles is seeking an experienced engineer to lead verification planning for complex systems. The role involves developing UVM environments and ensuring design specifications are met. Candidates should have 5–8 years of ASIC/SoC verification experience and expertise in System Verilog and UVM.

Join us to help shape the future of space exploration while enjoying competitive compensation and comprehensive benefits.

Qualifications

• 5–8+ years of ASIC/SoC verification experience.
• Deep hands-on expertise in System Verilog and UVM.
• Strong understanding of verification planning, assertions, and coverage closure.
• Experience verifying complex digital control and datapath logic.

Responsibilities

• Lead verification planning and execution for complex blocks or subsystems.
• Develop sophisticated UVM environments and verification strategies.
• Drive functional coverage closure and verification signoff readiness.
• Mentor junior engineers in verification standard processes.

Skills

ASIC/SoC verification experience

System Verilog

UVM

Debugging capability

Verification planning

Education

BS or MS in Electrical Engineering, Computer Engineering, or related field

Job description

Blue Origin in Los Angeles is seeking an experienced engineer to lead verification planning for complex systems. The role involves developing UVM environments and ensuring design specifications are met. Candidates should have 5–8 years of ASIC/SoC verification experience and expertise in System Verilog and UVM.

Join us to help shape the future of space exploration while enjoying competitive compensation and comprehensive benefits.