Space-Grade ASIC Verification Engineer

Blue Origin; Seattle (WA); On-site; USD 129,000 - 181,000; Full time

Benefits offered by this job

Stock Options for regular employees

Paid Time Off

401(k) with company match

Education Support Program

Job summary

Blue Origin is seeking an engineer to contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs, and to support module- and subsystem-level verification using UVM. The role involves writing test plans, coverage definitions, and debugging RTL/testbenches under guidance from senior engineers.

The successful candidate will document design intent, verification results, and test coverage, while learning industry-standard methodologies and collaborating with a

Qualifications

• BS or MS in Electrical/Computer Engineering, Computer Engineering, or related technical field (completed or in final year).
• Coursework or project experience with Verilog/SystemVerilog RTL design or verification.
• Understanding of digital logic design fundamentals (combinational/sequential logic, FSMs, timing).
• Familiarity with basic verification concepts (testbenches, simulation, coverage).
• Strong problem-solving skills and attention to detail.
• Effective communication and ability to work in a collaborative team environment.

Responsibilities

• Contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs.
• Support module-level and subsystem-level verification using SystemVerilog/UVM.
• Write test plans and functional coverage definitions under guidance from senior team members.
• Assist with CDC/RDC/LINT checks and clean-up.
• Participate in code coverage and functional coverage closure activities.
• Help develop assertions, protocol monitors, and scoreboards for testbenches.
• Support integration and verification of external IP (e.g., bus fabrics, standard interfaces).
• Learn and apply industry-standard verification methodologies (UVM, formal verification basics).
• Debug RTL and testbench issues with guidance from senior engineers.
• Document design intent, verification results, and test coverage.

Skills

Verilog/SystemVerilog

RTL design

Verification

UVM

Test plans

Debug RTL

Team collaboration

Education

BS or MS in Electrical/Computer Engineering

Tools

VCS

Xcelium

Questa

Formal tools

Job description

Blue Origin is seeking an engineer to contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs, and to support module- and subsystem-level verification using UVM. The role involves writing test plans, coverage definitions, and debugging RTL/testbenches under guidance from senior engineers.

The successful candidate will document design intent, verification results, and test coverage, while learning industry-standard methodologies and collaborating with a