Space ASIC Verification Engineer

Blue Origin; San Francisco (CA); On-site; USD 129,000 - 181,000; Full time

Benefits offered by this job

Medical, dental, vision

401(k) with company match

Paid time off and holidays

Education Support Program

Job summary

Blue Origin is seeking an early-career engineer to contribute to Verilog/SystemVerilog design and verification of digital blocks within SoCs. You will support module- and subsystem-level verification using UVM and help write test plans and coverage definitions under guidance from senior engineers.

You will also learn and apply industry-standard verification methodologies, assist with CDC/RDC/LINT checks, and document design intent and verification results as part of a collaborative team

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or related technical field (completed or in final year).
• Coursework or project experience with Verilog/SystemVerilog RTL design or verification.
• Understanding of digital logic design fundamentals (combinational/sequential logic, FSMs, timing).
• Familiarity with basic verification concepts (testbenches, simulation, coverage).
• Strong problem-solving skills and attention to detail.
• Effective communication and ability to work in a collaborative team environment.

Responsibilities

• Contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs
• Support module-level and subsystem-level verification using SystemVerilog/UVM
• Write test plans and functional coverage definitions under guidance from senior team members
• Assist with CDC/RDC/LINT checks and clean-up
• Participate in code coverage and functional coverage closure activities
• Help develop assertions, protocol monitors, and scoreboards for testbenches
• Support integration and verification of external IP (e.g., bus fabrics, standard interfaces)
• Learn and apply industry-standard verification methodologies (UVM, formal verification basics)
• Debug RTL and testbench issues with guidance from senior engineers
• Document design intent, verification results, and test coverage

Skills

Verilog/SystemVerilog

Digital logic fundamentals

UVM testbench concepts

Debugging expertise

Communication skills

Collaboration

Education

BS or MS in Electrical Engineering / Computer Engineering

Tools

VCS

Questa

Xcelium

Job description

Blue Origin is seeking an early-career engineer to contribute to Verilog/SystemVerilog design and verification of digital blocks within SoCs. You will support module- and subsystem-level verification using UVM and help write test plans and coverage definitions under guidance from senior engineers.

You will also learn and apply industry-standard verification methodologies, assist with CDC/RDC/LINT checks, and document design intent and verification results as part of a collaborative team