ASIC Verification Design Intern — Fast-Paced, High-Impact

ForwardEdge ASIC LLC; Saint Paul (MN); Vor Ort; USD 25.000 - 39.000; Vollzeit

Benefits dieser Stelle

Mentorship

Hands-on project experience

Competitive compensation

Zusammenfassung

ForwardEdge ASIC LLC in Saint Paul, MN is seeking an ASIC Design Verification Engineer Intern to support verification of ASIC and FPGA designs. You will work under experienced engineers to build verification environments and run tests.

Candidates pursuing a degree in electrical or computer engineering, with strong VLSI and digital logic coursework, and programming skills in Python or similar languages, are encouraged to apply. U.S. citizenship is required.

Qualifikationen

• Pursuing a bachelor’s or master’s degree in electrical or computer engineering.
• Strong coursework in VLSI design and digital logic.
• Proficiency in Python or similar object-oriented languages.
• Excellent communication and teamwork in a fast-paced environment.
• US citizenship is required.

Aufgaben

• Verify ASIC and FPGA designs across products.
• Create verification environments using SystemVerilog.
• Understand block-to-top UVM constrained random environments.
• Apply functional coverage, assertions, debug and formal verification.
• Collaborate with digital design engineers to ensure coverage.
• Automate processes with scripting (Python, Perl, TCL).

Kenntnisse

SystemVerilog

Python

Digital logic

VLSI design

Communication

Teamwork

US citizenship

Ausbildung

Bachelor's or Master's in Electrical/Computer Engineering

Jobbeschreibung

ForwardEdge ASIC LLC in Saint Paul, MN is seeking an ASIC Design Verification Engineer Intern to support verification of ASIC and FPGA designs. You will work under experienced engineers to build verification environments and run tests.

Candidates pursuing a degree in electrical or computer engineering, with strong VLSI and digital logic coursework, and programming skills in Python or similar languages, are encouraged to apply. U.S. citizenship is required.