Remote FPGA/ASIC Verification Engineer

Actalent; Saint Paul (MN); Remote; USD 110,000 - 185,000; Full time

Benefits offered by this job

401k

Health care

Bonus potential

Job summary

Actalent in Saint Paul, MN, is seeking a Design Verification Engineer to verify ASIC, SoC, IP, subsystem, and FPGA designs. You will develop testbenches, create tests, run simulations, and debug failures under senior guidance.

This hands-on role offers mentorship and exposure to modern verification methodologies, EDA tools, scripting, and the path from specification to verification closure. Collaborative work with design, firmware, and project teams is expected.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related technical field with 3+ years experience.
• Basic understanding of digital logic, RTL concepts, and hardware description languages.
• Exposure to SystemVerilog, Verilog, VHDL, or other HDL/verification languages.
• Familiarity with simulation, debugging, test development, or verification concepts.
• Basic scripting or programming experience in Python, Perl, Tcl, shell, C, or C++.
• Strong analytical and problem-solving skills.
• Willingness to learn modern ASIC verification methodologies including UVM, constrained-random verification, assertions, and coverage-driven verification.

Responsibilities

• Support verification activities for ASIC, SoC, IP, subsystem, and FPGA designs.
• Develop and maintain verification components using SystemVerilog and UVM where applicable.
• Create and run directed and constrained-random tests to verify design functionality.
• Assist in developing testbench components such as drivers, monitors, scoreboards, checkers, sequences, and coverage models.
• Analyze design specs and work with senior engineers to understand verification requirements.
• Run simulations and regressions using industry-standard EDA tools.
• Debug test failures using simulation logs, waveforms, and assertions.

Skills

SystemVerilog

UVM

Python

Verilog

Testbench

Debugging

Simulation

Education

Bachelor's or Master's in EE/CE

Tools

EDA tools

Simulation tools

Job description

Actalent in Saint Paul, MN, is seeking a Design Verification Engineer to verify ASIC, SoC, IP, subsystem, and FPGA designs. You will develop testbenches, create tests, run simulations, and debug failures under senior guidance.

This hands-on role offers mentorship and exposure to modern verification methodologies, EDA tools, scripting, and the path from specification to verification closure. Collaborative work with design, firmware, and project teams is expected.