ASIC/SoC Verification Engineer

Prodapt; Mountain View (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Prodapt is seeking an experienced ASIC/SoC Verification Engineer in Mountain View, CA. The role focuses on verifying RF payloads, satellite processors, and high-speed communication systems, using SystemVerilog and UVM in scalable testbenches.

You will debug RTL, verify PCIe Gen3–6, and ensure protocol conformance across IP and SoC levels. Ideal candidates hold a Bachelor’s or Master’s in Electronics, Communications, or VLSI and possess strong scripting (Python/Perl/Tcl) for automation, along

Qualifications

• Define, develop, and execute comprehensive verification plans at IP and SoC levels.
• Experience with RF payloads, satellite processors, and communication systems is desired.
• Strong SystemVerilog/UVM expertise and high-speed protocol verification.

Responsibilities

• Define, develop, and execute verification strategies for IP and SoC.
• Architect scalable UVM testbenches for PCIe and DMA sub-systems.
• Verify PCIe Gen3–6 controller layers, including Physical, Data Link, and Transaction.
• Develop and verify high-speed protocols ensuring strict spec compliance.
• Apply UPF/CPF for low-power verification and performance checks.
• Debug RTL, triage failures, and collaborate with design teams.
• Set up gate-level simulations with timing annotations when needed.
• Work on RF payloads, satellite processors, and related comm systems.

Skills

SystemVerilog

UVM

PCIe Gen3-6

DMA

Python

Perl

Tcl

RTL debugging

Education

Bachelor's or Master's in Electronics/Communications/VLSI

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Job description

Prodapt is the largest specialized player in the Connectedness industry. As an AI-first strategic technology partner, Prodapt provides consulting, business reengineering, and managed services for the largest telecom and tech enterprises building networks and digital experiences of tomorrow. A ServiceNow-invested company, Prodapt has been recognized by Gartner as a Large, Telecom-Native, Regional IT Service Provider. Prodapt’s ASIC Services is a leading provider of SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation, DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup. Analog mask layout. Our embedded services include device drivers, RTOS porting, and board bring-up. A “Great Place To Work® Certified™” company, Prodapt employs over 6,000 technology and domain experts in 30+ countries. Prodapt is part of the 130-year-old business conglomerate The Jhaver Group, which employs over 32,000 people across 80+ locations globally.

We’re looking for an experienced ASIC/SoC Verification Engineer with 8+ years hands on experience to join our team and work on next-generation RF payloads, satellite processors, and communication systems in Mountain View, CA.

If you enjoy building verification environments from the ground up, debugging complex RTL issues, and working with high-speed interfaces such as PCIe, we’d love to hear from you!

• Verification Strategy: Define, develop, and execute comprehensive verification plans at both IP and SoC levels.
• Domain: Work on RF payloads, satellite processors, and communication systems.
• Testbench Architecture: Architect scalable, reusable, constrained-random verification environments from scratch using SystemVerilog and UVM.
• PCIe Sub-System Verification: Verify PCIe Gen 3–6 controller layers — Physical, Data Link, and Transaction — along with high-throughput DMA engines configured as Endpoint or Root Complex.
• Protocol Verification: Implement and verify high-speed industry-standard protocols while ensuring strict compliance with specifications.
• Power/Performance Verification: Apply low-power verification methodologies using UPF/CPF and/or perform performance verification.
• Debug & Triaging: Debug complex test failures, identify RTL root causes, and collaborate closely with design engineers to resolve issues.
• Gate-Level Simulation: Set up and execute gate-level simulations (GLS) with or without timing annotations.
• Bachelor’s or Master’s degree in Electronics, Communications, VLSI, or a related engineering discipline.
• Strong experience with SystemVerilog and UVM.
• Experience verifying PCIe Gen 3–6, DMA, and high-speed protocols.
• Exposure to RF payloads, satellite processors, or communication systems is highly desirable.
• Strong scripting/automation skills using Python, Perl, or Tcl.
• Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
• Strong analytical, debugging, and problem-solving skills.