ASIC/SoC Physical Design Engineer - RTL-to-GDSII Pro

Zachary Piper Solutions; Raleigh (NC); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

401(k)

Paid time off

Job summary

Piper Companies is seeking a Physical Design Engineer to sit onsite in RTP, NC to support advanced semiconductor development for a leading organization in the semiconductor industry. The Physical Design Engineer will drive physical implementation across ASIC and SoC designs from RTL through tapeout, partnering with cross-functional engineering teams to achieve timing, power, and performance goals.

Responsibilities include RTL-to-GDSII flow, STA, physical verification, and power integrity, with

Qualifications

• 5+ years of experience in ASIC/SoC physical design and implementation.
• Hands-on experience with Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, Tempus and Calibre verification tools.
• Strong understanding of RTL-to-GDSII flow, STA, physical verification, low-power methodologies and timing closure.

Responsibilities

• Execute full RTL-to-GDSII physical design flow including synthesis, floor planning, place and route, CTS, and timing closure.
• Perform static timing analysis, ECO implementation, and MMMC timing signoff activities.
• Conduct physical verification including DRC, LVS, antenna checks, and design signoff.
• Analyze and resolve signal integrity, IR drop, electromigration, and power integrity challenges.
• Collaborate with RTL, verification, DFT, and system teams to optimize design quality, performance, and power.

Skills

Tcl

Perl

Python

Linux/Unix

Design flow automation

Tools

Cadence Innovus

Synopsys ICC2

Fusion Compiler

PrimeTime

Tempus

Calibre

Job description

Piper Companies is seeking a Physical Design Engineer to sit onsite in RTP, NC to support advanced semiconductor development for a leading organization in the semiconductor industry. The Physical Design Engineer will drive physical implementation across ASIC and SoC designs from RTL through tapeout, partnering with cross-functional engineering teams to achieve timing, power, and performance goals.

Responsibilities include RTL-to-GDSII flow, STA, physical verification, and power integrity, with