Hybrid Physical Design Engineer: ASIC/SoC Expert (RTP/NC)

Piper Companies; Raleigh (NC); Hybrid; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

401(k)

Paid time off

Job summary

Piper Companies seeks a Physical Design Engineer to sit onsite in RTP, NC to support advanced semiconductor development for a leading organization in the semiconductor industry. The Physical Design Engineer will drive physical implementation from RTL through tapeout, partnering with cross-functional teams to meet timing, power and performance goals.

The role involves full RTL-to-GDSII flow, STA, physical verification, and collaboration with RTL, verification, DFT, and system groups to optimize

Qualifications

• 5+ years of experience in ASIC/SoC physical design and implementation for advanced semiconductor products.
• Hands-on with Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, Tempus, and Calibre verification tools.
• Strong RTL-to-GDSII flow knowledge, STA, physical verification, and low-power methodologies.
• Experience with FinFET nodes and hierarchical/full-chip integration.
• Proficiency in Tcl, Perl, Python, Linux/Unix environments; design flow automation.

Responsibilities

• Execute full RTL-to-GDSII physical design flow including synthesis, floor planning, place and route, CTS, and timing closure.
• Perform static timing analysis, ECO implementation, and MMMC timing signoff activities.
• Conduct physical verification including DRC, LVS, antenna checks, and design signoff.
• Analyze and resolve signal integrity, IR drop, electromigration, and power integrity challenges.
• Collaborate with RTL, verification, DFT, and system teams to optimize design quality, performance, and power.

Skills

RTL-to-GDSII flow

Timing closure

Low-power design

Signal integrity

Linux scripting

Tools

Cadence Innovus

Synopsys ICC2/Fusion Compiler

PrimeTime

Tempus

Calibre

Job description

Piper Companies seeks a Physical Design Engineer to sit onsite in RTP, NC to support advanced semiconductor development for a leading organization in the semiconductor industry. The Physical Design Engineer will drive physical implementation from RTL through tapeout, partnering with cross-functional teams to meet timing, power and performance goals.

The role involves full RTL-to-GDSII flow, STA, physical verification, and collaboration with RTL, verification, DFT, and system groups to optimize