ASIC RTL Design Engineer

Xcelerium

Irvine (CA)

On-site

USD 80,000 - 100,000

Full time

14 days+

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Benefits offered by this job

Bonus eligibility

Equity

Comprehensive benefits

Job summary

Xcelerium is seeking a New Grad ASIC RTL Design Engineer to contribute to the design of advanced ASIC technology for Physical AI Compute. This on-site full-time position is open to recent graduates in Electrical Engineering or Computer Engineering.

The role involves collaboration with expert chip designers, covering the full hardware development lifecycle from artifacts to RTL design and performance analysis. Strong fundamentals in digital logic, RTL development in Verilog or SystemVerilog, and enthusiasm for complex systems are essential.

Join a pioneering team at Xcelerium as we advance the field of real-time AI computing.

Qualifications

Strong fundamentals in digital logic, synchronous design, finite state machines.
Experience writing RTL in Verilog or SystemVerilog through relevant projects.
Ability to write scripts or software in languages like Python, C, or C++.

Responsibilities

Contribute to the ASIC/SoC development lifecycle across various phases.
Help design hardware structures for real-time AI workloads.
Participate in verification activities and design tradeoffs.

Skills

Digital logic

RTL in Verilog/SystemVerilog

Scripting in Python/C/C++

Debugging skills

Education

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field

Tools

Git

Linux development environments

Job description

New Grad -ASIC RTL Design Engineer — Physical AI Compute

About Xcelerium

Xcelerium is building the computer foundation for real-time Physical AI — intelligent systems that must process rich sensor data, make decisions, and act under demanding real-world constraints of latency, bandwidth, power, size, and reliability.

We are developing a differentiated compute platform for workloads that span signal processing, AI/ML, linear algebra, optimization, control, and real-time decision-making. Our technology is designed for applications such as autonomous systems, robotics, wireless infrastructure, aerospace and defense, industrial automation, and edge AI.

Xcelerium is led by an experienced team of computer architects, chip designers, and technology leaders with deep backgrounds in advanced SoCs, wireless, AI/ML, compute, and high-volume semiconductor products. This is an opportunity to join a team building advanced silicon for a new class of real-world AI compute.

Location

Primary location: Irvine, CA

This is an on-site role.

Job Type

Full-time, new graduate / entry-level

Compensation

The expected base salary range for this role is $80K - $100K, plus eligibility for bonus/equity/benefits. Final compensation will depend on location, experience, and qualifications.

About the Role

As a New Grad ASIC RTL Design Engineer — Physical AI Compute, you will contribute to the design and implementation of advanced ASIC and SoC technology for Xcelerium’s next-generation compute platform.

This is a broad silicon design role for an exceptional early-career engineer who wants exposure to the full hardware development lifecycle — from architecture exploration and microarchitecture to RTL design, verification, physical design feedback, performance analysis, and silicon-quality design closure.

You will work with leading computer architects and expert chip designers to help build production silicon for a new class of real-time Physical AI compute.

We are looking for highly curious, technically strong, and ambitious engineers who want to learn quickly, contribute deeply, and grow into future leaders in computer architecture and silicon design.

What You’ll Do

Contribute across the ASIC/SoC development lifecycle, including architecture exploration, microarchitecture, RTL design, verification, implementation feedback, and design closure.
Help translate real-time Physical AI workload requirements into efficient hardware structures, datapaths, control logic, memory systems, and interconnects.
Design and implement clean, synthesizable RTL in SystemVerilog or Verilog.
Participate in high-performance datapath design for compute-intensive, bandwidth-intensive, and latency-sensitive workloads.
Evaluate design tradeoffs involving latency, throughput, power, area, timing, programmability, reliability, and implementation complexity.
Work hands-on with simulation, debug, lint, CDC, synthesis, static timing analysis, power analysis, and other ASIC development flows.
Participate in verification activities, including test plan reviews, debug, assertions, observability, and design-quality improvements.
Use physical design feedback to improve timing, frequency, area, power, and robustness on advanced silicon process technologies.
Write clear design documentation, interface specifications, implementation notes, and debug summaries.
Participate in technical design reviews and learn how advanced silicon is specified, designed, verified, implemented, and brought to production.

What We’re Looking For

B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent hands‑on project or internship experience.
Strong fundamentals in digital logic, synchronous design, finite state machines, pipelining, timing, and computer architecture.
Experience writing RTL in Verilog or SystemVerilog through coursework, research, internship, FPGA work, ASIC projects, or personal projects.
Familiarity with processor architecture, memory hierarchy, caches, buses, interconnects, datapaths, or SoC design concepts.
Ability to write scripts or software in at least one language such as Python, C, C++, assembly, or a similar language.
Strong debugging skills and the ability to reason carefully about hardware behavior.
Clear written and verbal communication skills, including the ability to document design intent and explain technical tradeoffs.
High ownership, intellectual curiosity, and a desire to learn quickly from experienced engineers.

Preferred Qualifications

Experience with CPU, accelerator, memory subsystem, cache controller, DMA, NoC, bus fabric, high-performance datapath, or SoC design projects.
Familiarity with RISC‑V, ARM, MIPS, or another processor ISA.
Exposure to ASIC or FPGA flows, including simulation, lint, CDC, synthesis, static timing analysis, power analysis, place‑and‑route feedback, or FPGA implementation.
Exposure to UVM, SystemVerilog assertions, constrained-random verification, formal verification, or testbench development.
Interest in real-time systems, robotics, autonomous systems, edge AI, AI acceleration, signal processing, or high-performance embedded compute.
Experience with Chisel, SpinalHDL, Bluespec, or another hardware construction language.
Experience with Git, Linux development environments, shell scripting, Make/CMake, or EDA tool automation.
Research, internship, tapeout, open-source hardware, robotics, accelerator, VLSI, or advanced computer architecture project experience.

Why Join Xcelerium

Work with leading computer architects and expert chip designers on advanced production silicon.
Learn the complete path from architecture concept to real hardware implementation.
Contribute to a differentiated compute platform for real-time Physical AI and autonomy.
Gain hands‑on experience across RTL design, verification, performance analysis, physical design feedback, and silicon-quality closure.
Work on high-performance datapaths and digital logic where latency, throughput, power, area, and timing all matter.
Build experience with advanced process technologies and modern ASIC implementation tradeoffs.
Join a team that values technical depth, first‑principles thinking, clean implementation, thoughtful documentation, and high ownership.
Xcelerium is an equal opportunity employer. We are committed to building a team that reflects a wide range of backgrounds, experiences, and perspectives. We encourage candidates who are excited by our mission and believe they can contribute to apply.
This job requires US work authorization
This job is open to candidates with Curricular Practical Training (CPT)
This job is open to candidates with Optional Practical Training (OPT)