ASIC Physical Design Engineer, Netlisting - New College Grad 2026

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in California is seeking a candidate for the physical design of high-frequency CPUs, GPUs and SoCs, focusing on netlist tasks, equivalence checking, clock-domain crossing and MTBF analysis.

Requirements include a Master’s or PhD in Electrical or Computer Engineering, hands-on RTL/logic design for timing closure, experience with EDA tools (Synopsys or Cadence), and scripting in Perl, TCL, Make or Python. Applications accepted until May 11, 2026.

Qualifications

• Master’s or PhD in Electrical or Computer Engineering (or equivalent).
• Experience in logic equivalence checking/formal verification from RTL to tapeout with industry tools.
• Understanding of hardware architecture and RTL/logic design for timing closure.
• Experience in clock-domain-crossing checking, MTBF analysis with EDA tools or in-house tools.
• Background with logic synthesis at block or full-chip level, project execution or flow development.
• Familiarity with industry standard EDA tools.
• Experience in programming/scripting languages such as Perl, TCL, Make, Python, etc.

Responsibilities

• Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block/cluster/full-chip level with focus on netlist-related checks and ECO generation.
• Help in ECO generation and implementation.

Skills

Logic equivalence checking

Formal verification

RTL/logic design

Clock-domain-crossing

MTBF analysis

Logic synthesis

Programming/scripting

Education

Master's degree in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Tools

Synopsys

Cadence

Job description

What you’ll be doing:

• Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.
• Help in ECO generation and implementation.

What we need to see:

• Master’s or PhD degree in Electrical or Computer Engineering (or equivalent experience).
• Shown knowledge in logic equivalence checking/Formal Verification required from RTL to tapeout with industry-standard tools.
• Understanding of hardware architecture and hands‑on skills in RTL/logic design for timing closure.
• Experience in clock-domain-crossing checking, MTBF analysis, either with EDA tools (i.e., Synopsys or Cadence) or in-house tools.
• Background with logic synthesis at either block or full-chip level, at project execution and/or flow development.
• In‑depth knowledge of industry standard EDA tools in related fields.
• Experience in programming and scripting languages, such as Perl, TCL, Make, Python, etc.

Ways to stand out from the crowd:

• Experience in logic synthesis and equivalence checking/FV. Familiarity with industry tools and flow.
• Strong hands‑on debugging capability and problem‑solving skills.
• Experience improving workflows and productivity through effective AI utilization is a plus.

Base salary will be determined based on location, experience, and the pay of employees in similar positions. The base salary range is $116,000 - $189,750 for Level 2, and $136,000 - $218,500 for Level 3.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until May 11, 2026.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. We highly value diversity in our current and future employees, and we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.