ASIC Physical Design Engineer — Block-Level PPA

Apple, Inc.; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

APPLE INC in Austin, Texas is seeking a hardware/ASIC engineer to drive block-level physical design for GPU IPs. You will work through floor planning, placement, clock tree synthesis, and routing, ensuring timing closure and power efficiency across the design.

Responsibilities include using Innovus/IC Compiler for P&R, Primetime for timing, Caliber for DRC/LVS, Voltus for electrical analysis and scripting with Perl/Tcl/Python to automate design metrics. Collaboration with RTL teams is essential.

Qualifications

• Master's degree in Electrical Engineering or related field with 2 years of relevant experience.
• Experience with MOS, VLSI circuit design, and physical design fundamentals.
• Proficient in block-level floor planning, placement, routing, and timing closure.
• Proficient with Innovus or IC Compiler for floor planning and P&R.
• Experience with Primetime for timing closure, Caliber for DRC/LVS, Voltus for electrical analysis.
• Scripting using Perl, Tcl, or Python to parse reports and automate tasks.

Responsibilities

• Work on GPU block level physical design from floor planning to routing and timing.
• Perform low-power techniques including clock gating and multi-voltage designs.
• Ensure DRC/LVS compliance and electrical analysis.
• Collaborate with RTL teams to drive floor planning and physical implementation.
• Analyze and optimize PPA for performance, power, and area.

Skills

MOS & VLSI fundamentals

Physical design concepts

Timing closure

P&R familiarity

Scripting (Perl, TCL, Python)

Floorplanning & Place & Route

Innovus

IC Compiler

Primetime

Caliber

Voltus

Genus/DC Compiler

Education

Master's degree in Electrical Engineering or related field

Tools

Innovus

IC Compiler

Primetime

Caliber

Voltus

Genus

DC Compiler

Job description

APPLE INC in Austin, Texas is seeking a hardware/ASIC engineer to drive block-level physical design for GPU IPs. You will work through floor planning, placement, clock tree synthesis, and routing, ensuring timing closure and power efficiency across the design.

Responsibilities include using Innovus/IC Compiler for P&R, Primetime for timing, Caliber for DRC/LVS, Voltus for electrical analysis and scripting with Perl/Tcl/Python to automate design metrics. Collaboration with RTL teams is essential.