Lead Physical Design Engineer - AI Graphics IP

Advanced Micro Devices, Inc.; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Advanced Micro Devices, Inc. in Austin, TX is seeking an experienced physical design engineer to own and drive complex blocks for next-generation graphics IP and AI data center chips.

You will collaborate with RTL and other engineering teams through floorplanning, synthesis, placement, CTS, routing, timing, extraction, and signoff, delivering designs within tight performance and power targets. The role offers leadership opportunities, mentoring responsibilities, and the chance to influence

Qualifications

• Strong experience in physical design for high-performance semiconductors.
• Experience with RTL blocks timing closure and signoff.
• Proficiency with floorplanning, synthesis, placement, CTS, routing and verification.
• Experience establishing design methodologies and IP integration.

Responsibilities

• Own the physical design of complex graphics IP blocks and meet performance, power and area targets.
• Collaborate with RTL teams to identify bottlenecks early in the project.
• Lead floorplanning, synthesis, placement, CTS, routing, extraction, timing closure, and signoff.
• Support DRC/LVS, crosstalk, EM/IR analyses through final signoff.
• Develop and improve design flows and methodologies.
• Provide technical leadership and mentoring to engineers.
• Collaborate across distributed teams to deliver projects.

Skills

Physical design

Timing closure

RTL collaboration

Mentoring engineers

Automation scripting

Education

Bachelor's or Master's in Electronics/Electrical Engineering

Tools

Synopsys ICC2

ICC

Fusion Compiler

PrimeTime

StarRC

Mentor Calibre

Cadence Innovus

Genus

Apache RedHawk

Job description

Advanced Micro Devices, Inc. in Austin, TX is seeking an experienced physical design engineer to own and drive complex blocks for next-generation graphics IP and AI data center chips.

You will collaborate with RTL and other engineering teams through floorplanning, synthesis, placement, CTS, routing, timing, extraction, and signoff, delivering designs within tight performance and power targets. The role offers leadership opportunities, mentoring responsibilities, and the chance to influence