ASIC Research Engineer- Front-End Digital Design

University of Southern California

Arlington (VA)

On-site

USD 115,000 - 140,000

Full time

7 days ago
Be an early applicant

A complete application in a minute

Tailored resume and cover letter, ready to send.

Get past ATS filters

Job summary

University of Southern California’s Information Sciences Institute in Arlington, VA is hiring an ASIC Research Engineer for front-end digital design. You will design and verify RTL models of CPUs, memories and accelerators using Verilog, SystemVerilog or VHDL, and collaborate with MOSIS 2.0 service and third-party IP cores.

The role requires a degree in Computer or Electrical Engineering with 3+ years experience (or a Master’s) and strong Linux, scripting, and revision control skills.

Qualifications

  • Bachelor’s degree in Computer or Electrical Engineering; >3 years experience or Master’s degree
  • RTL/Verilog/SystemVerilog/VHDL RTL design experience
  • Solid understanding of computer architecture and microarchitecture
  • Experience with Linux and scripting; revision control tools

Responsibilities

  • Design and verify RTL models of CPUs, memories and accelerators.
  • Collaborate with MOSIS 2.0 service and integrate third-party IP cores.
  • Engage with sponsor programs (DARPA, IARPA, CHIPS Act) and work in a fast-moving research setting.

Skills

RTL design
Verilog
SystemVerilog
VHDL
Computer architecture
Microarchitecture
Linux
Scripting
Revision control

Education

Bachelor’s degree in Computer/Electrical Engineering
Master’s degree

Tools

EDA tools
FPGAs

Job description

ASIC Research Engineer- Front-End Digital Design### ASIC Research Engineer- Front-End Digital DesignApply: Arlington, VA: Full time: Posted Today: REQ20182054USC’s **Information Sciences Institute (ISI)**, a unit of the university’s Viterbi School of Engineering, is a world leader in the research and development of advanced information processing, computing, communications and artificial intelligence technologies. ISI’s 400 faculty, professional staff and graduate students carry out extraordinary information sciences research at three distinct locations - Arlington, VA; Marina Del Rey, CA; and Waltham, MA. ISI’s CS&T Division has an opening in Arlington, VA for an **ASIC Research Engineer – Front-end Digital Design**, to perform digital design of advanced ASIC prototypes addressing problems of national importance. The Engineer will work with a cutting-edge team to design and verify register-transfer level (RTL) models of CPUs, memories, and accelerators for applications such as communications, signal processing, and security. The Engineer will have opportunities to collaborate with ISI’s MOSIS 2.0 service, integrate third-party IP cores, and gain experience working with top research sponsors such as DARPA, IARPA, and the CHIPS Act. The position provides a collaborative, flexible university setting with rich learning and growth opportunities. The Engineer will gain experience in a fast-moving research setting and work toward a better and more secure future. **The work will be based in ISI's Arlington, VA office.**# # **Minimum Qualifications** * Ability to handle Controlled Unclassified Information (CUI). Per U.S. government regulations, eligibility to handle CUI requires **U.S. Citizenship or Permanent Residency.*** Degree in Computer Engineering, Electrical Engineering, or related field* Bachelor’s degree with >3 years of experience, or Master’s degree* Demonstrated excellence creating digital designs with Verilog, System Verilog, or VHDL RTL* Solid understanding of computer architecture and microarchitecture* Demonstrated skills with EDA tools, scripting, revision control# # **Preferred Qualifications** * Experience using logic synthesis and timing tools* Familiarity with digital design verification* Familiarity with performance modeling* Familiarity with agile hardware design methodologies* Experience with AI-assisted workflows* Experience using FPGAs* Effective at verbal communication and giving clear explanations The annual base salary range for this position is $115,000 to $140,000. When extending an offer of employment, the University of Southern California considers factors such as (but not limited to) the scope and responsibilities of the position, the candidate’s work experience, education/training, key skills, internal peer equity, federal, state, and local laws, contractual stipulations, grant funding, as well as external market and organizational considerations. # **Why work at ISI** * Work on exciting and engaging projects that have real-life impact.* Small project team environment allows for involvement across entire project lifecycle.* A quality work-life balance.* Opportunities for free, top-tier university education for you and your children.* Great benefits - medical to matched retirementMinimum Education: Bachelor's degree, combined experience/education as substitute for minimum education Minimum Experience: 3 years Preferred Education: Master's degree Preferred Experience: 5 years Required Skills: Experience with Linux. Preferred Skills: Proven leadership ability. Experience with artificial intelligence, very large-scale integration design, machine learning, deep learning (e.g., TensorFlow, PyTorch, HuggingFace), and Dockerization. **USC is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability, or any other characteristic protected by law or USC policy. USC observes affirmative action obligations consistent with state and federal law. USC will consider for employment all qualified applicants with criminal records in a manner consistent with applicable laws and regulations, including the Los Angeles County Fair Chance Ordinance for employers and the Fair Chance Initiative for Hiring Ordinance, and with due consideration for patient and student safety. Please refer to the****Background Screening Policy Appendix D****for specific employment screen implications for the position for which you are applying.****We provide reasonable accommodations to applicants and employees with disabilities. Applicants with questions about access or requiring a reasonable accommodation for any part of the application or hiring process should contact USC Human Resources by phone at (213) 821-8100, or by email at uschr@usc.edu. Inquiries will be treated as confidential to the extent permitted by law.**
Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Senior ASIC Research Engineer – Front-end Digital Design
Senior ASIC Research Engineer – Front-end Digital Design

University of Southern California • Arlington (VA)

On-site
USD 140,000 - 170,000
ASIC Research Engineer- Front-End Digital Design
ASIC Research Engineer- Front-End Digital Design

Aimlroles • Virginia

On-site
USD 115,000 - 140,000
Free university education for you and
Education benefits for you and your/
Great benefits – medical to matched退休
Senior ASIC Research Engineer – Front-end Digital Design
Senior ASIC Research Engineer – Front-end Digital Design

Aimlroles • Virginia

On-site
USD 140,000 - 170,000
Education benefits for family
Medical and retirement benefits
Hybrid work flexibility
FPGA Design Engineer
FPGA Design Engineer

University of Southern California • Arlington (VA)

Hybrid
USD 115,000 - 140,000
Senior FPGA Design Engineer
Senior FPGA Design Engineer

University of Southern California • Arlington (VA)

Hybrid
USD 140,000 - 170,000
Hybrid work options
Senior ASIC Front-end RTL Design Engineer – Research
Senior ASIC Front-end RTL Design Engineer – Research

Aimlroles • Virginia

On-site
USD 140,000 - 170,000
Education benefits for family
Medical and retirement benefits
Hybrid work flexibility
Research Computer Scientist, Reconfigurable Computer Architecture
Research Computer Scientist, Reconfigurable Computer Architecture

University of Southern California • Arlington (VA)

On-site
USD 140,000 - 180,000
ASIC Front-End RTL Engineer for Digital Design
ASIC Front-End RTL Engineer for Digital Design

Aimlroles • Virginia

On-site
USD 115,000 - 140,000
Free university education for you and
Education benefits for you and your/
Great benefits – medical to matched退休
EDA Infrastructure Engineer
EDA Infrastructure Engineer

University of Southern California • California

On-site
USD 157,000 - 180,000
Application Specific Integrated Circuit Design Engineer
Application Specific Integrated Circuit Design Engineer

The Richmond Group USA • San Jose (CA)

On-site
USD 171,000 - 209,000
Stock options
Annual bonus
Work-life balance