ASIC Engineer, Implementation - Timing

Meta; Sunnyvale (CA); On-site; USD 114,000 - 172,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta's Infrastructure Silicon team is seeking an ASIC Implementation Engineer focusing on timing to drive static timing analysis and timing closure for advanced process nodes in data center chips. You will collaborate across front-end and back-end to meet performance, power, and area targets at 7nm and beyond.

Responsibilities include creating timing constraints, conducting sign-off timing with PrimeTime, and guiding RTL and physical implementation optimizations.

Qualifications

• Experience with static timing analysis and timing closure.
• Experience developing and validating timing constraints for complex SoC designs.

Responsibilities

• Develop and maintain timing constraints (SDC) for complex SoC designs.
• Perform static timing analysis to identify setup/hold violations across blocks.
• Drive timing closure through collaboration with physical design engineers for placement, routing and_clock tree synthesis.
• Analyze timing paths across multiple clock domains and optimize RTL or physical implementations.
• Generate and validate timing reports for sign-off across corners including on-chip variation.

Skills

Python scripting

Tcl scripting

Perl scripting

Education

Bachelor's degree in Computer Science or Electrical Engineering

Tools

PrimeTime

Job description

Meta's Infrastructure Silicon team is seeking an ASIC Implementation Engineer specializing in timing to help design and deliver custom silicon for data center applications. In this role, you will drive static timing analysis and timing closure across complex System on Chip designs, working at the intersection of front-end and back-end implementation to ensure our infrastructure chips meet performance, power, and area targets at advanced process nodes.

ASIC Engineer, Implementation - Timing Responsibilities

• Develop and maintain timing constraints (SDC) for complex SoC designs, including clock definitions, input/output delays, multicycle paths, and false paths
• Perform static timing analysis using industry-standard sign-off tools to identify and resolve setup, hold, and clock skew violations across hierarchical design blocks
• Drive timing closure through collaboration with physical design engineers, providing guidance on placement, routing, and clock tree synthesis to meet timing targets
• Analyze and debug timing paths across multiple clock domains, identifying critical paths and recommending RTL or physical implementation optimizations
• Generate and validate timing reports for sign-off across process, voltage, and temperature corners, including on-chip variation analysis
• Develop and maintain timing exception methodologies and waiver processes in coordination with design and verification teams
• Contribute to the development and improvement of timing closure scripts and automation flows using scripting languages to increase efficiency and repeatability
• Interface with foundry and library teams to characterize and integrate timing libraries, including standard cells, memories, and hard IP
• Support design handoff between front-end and back-end teams by providing timing-aware synthesis netlists and constraint validation

Minimum Qualifications

• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
• Currently has a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 2+ years of experience in ASIC implementation with a focus on static timing analysis and timing closure
• Experience with industry-standard static timing analysis and sign-off tools such as PrimeTime or equivalent
• Experience developing and validating SDC timing constraints for complex SoC or IP designs
• Experience with logic synthesis tools and timing-driven optimization techniques
• Experience scripting in Python, Tcl, or Perl to automate timing analysis and reporting flows

Preferred Qualifications

• Experience with RTL design or synthesis using SystemVerilog or other hardware description languages
• Experience with timing closure at advanced process nodes (7nm or below), including on-chip variation and multi-corner multi-mode analysis
• Familiarity with physical design concepts such as placement, routing, and parasitic extraction as they relate to timing closure
• Experience with clock tree synthesis and clock network optimization in the context of timing sign-off

About Meta

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Meta is proud to be an Equal Employment Opportunity and Affme Act employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].

$114,000/year to $172,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.