ASIC Engineer, Foundry and IP

Meta; Austin (TX); On-site; USD 146,000 - 209,000; Full time

Job summary

Meta is building custom silicon to power AI infrastructure and immersive computing experiences in Austin, TX. The team seeks an experienced ASIC engineer to benchmark foundry technologies, drive PPA analysis, and contribute to test-chip design and validation for foundation IP and memory components.

Responsibilities include RTL-to-GDS design, transistor-level layout, and collaboration with foundry partners to optimize performance, power, and area for next-gen datacenter silicon.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 6+ years of experience in a foundry team driving PPA analysis and engineering benchmarking
• Deep understanding of CMOS device physics, digital circuit design, and advanced node layout constraints
• Proven track record of test chip tapeouts and end-to-end design ownership
• Expert-level command of Cadence Virtuoso, HSPICE, Spectre
• Working knowledge of synthesis, PnR, STA and PDV tools
• High proficiency in scripting with Python, TCL, Perl, or SKILL to automate large-scale evaluation pipelines and data analysis
• MS or PhD in electrical engineering (preferred)
• 8+ years of experience driving PPA analysis and optimization of foundational IPs
• Experience owning test chips as chip lead (preferred)
• Experience with DTCO optimization with foundry partners (preferred)
• Experience bringing sub-5nm to 2nm GAA test chips (preferred)

Responsibilities

• Analyze and benchmark foundry process offerings with physical design teams
• Drive early PPA evaluation of foundation IP drops
• Architect, design, and characterize high-performance standard cell libraries
• Run transistor-level simulations and manage library characterization flows
• Evaluate memory compilers based on PPA and trade-off metrics
• Participate in physical implementation and tape-out of silicon test chips

Skills

Cadence Virtuoso

HSPICE

Spectre

Python

TCL/Perl/SKILL

Education

Bachelor's degree in CS/CE or equivalent

MS or PhD in EE

Tools

Synthesis

PnR

STA

PDV

Job description

Summary:

Meta is building custom silicon to power the next generation of AI infrastructure and immersive computing experiences. The Infrastructure Silicon team is responsible for designing and delivering high-performance, power-efficient ASICs that underpin Meta's data center and AI workloads. We are looking for individuals with experience in foundry technology benchmarking and PPA analysis, stdcell circuit design and characterization, memory compiler PPA optimization and test chip design and testing.

Required Skills:

ASIC Engineer, Foundry and IP Responsibilities:

1. Analyze and benchmark foundry process offering with physical design teams to identify optimal technologies for product roadmaps
2. Drive early PPA evaluation of foundation IP drops by running preliminary PnR experiments to identify issues and opportunities for improvement
3. Architect, design, and characterize high-performance, low-power, and ultra-high-density standard cell libraries with foundry partners and Physical design teams
4. Run transistor-level simulations (SPICE), direct custom physical layouts, and manage automated library characterization flows
5. Evaluate, benchmark, and choose third-party memory compilers (SRAM, Register Files, ROM) based on rigorous PPA and trade-off metrics
6. Participate in physical implementation, and tape‑out of silicon test chips targeted at proving out new foundation IP, custom structures

Minimum Qualifications:

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
2. 6+ years of experience in a foundry team driving PPA analysis and engineering army benchmarking
3. Deep understanding of CMOS device physics, digital circuit design, and advanced node layout constraints
4. Proven track record of participating in test chip tapeouts. Hands‑on experience in owning end to end design and sign‑off of partitions on a test chip
5. Expert‑level command of design environments like Cadence Virtuoso, HSPICE, Spectre
6. Working knowledge of synthesis, PnR, STA and PDV tools to converge a block on a test chip
7. High proficiency in scripting with Python, TCL, Perl, or SKILL to automate large‑scale evaluation pipelines and data analysis

Preferred Qualifications:

Preferred Qualifications:

1. MS or PhD in electrical engineering
2. 8+ years of experience driving PPA analysis, selection and optimization of foundational IPs - Standard cells and memory compilers in particular
3. Experience owning test chips as chip lead is preferred
4. Experience driving DTCO optimization with foundry partners and design teams on advanced logic technologies is preferred
5. Experience in bringing multiple sub-5nm, 3nm, or 2nm GAA (Gate-All-Around) complex test chips from initial architecture through to validation

Public Compensation:

$146,000/year to $209,000/year + bonus + equity + benefits

Industry:

Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Aff… We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].