ASIC Engineer

Datum Technologies Group; San Jose (CA); On-site; USD 141,000 - 342,000; Full time

Job summary

An innovative firm is seeking a Mid-Senior level engineer to drive chip-package-system co-design and optimize signal integrity. This role involves defining power tree structures for High Performance Computing and running simulations focused on high-speed interfaces. Collaborating with cross-functional teams, the engineer will validate designs in the lab, ensuring performance meets expectations. This is a unique opportunity to contribute to cutting-edge technology in semiconductor manufacturing, with a competitive salary range reflecting the high demand for expertise in this field.

Qualifications

• 5+ years of experience in SIPI simulation and validation areas.
• Solid understanding of high-speed interface protocols like MIPI and PCIe.
• Experience with consumer hardware design and CAD tools.

Responsibilities

• Drive chip-package-system co-design for signal and power integrity.
• Validate high-speed interface and PDN impedance in lab settings.
• Develop detailed engineering test plans for SIPI validation.

Skills

SIPI simulation

high-speed interface protocols

computational electromagnetics

transmission line theory

Education

Bachelor or Master in Electrical Engineering

Bachelor or Master in Physics

Bachelor or Master in Mathematics

Tools

Cadecen Sigrity

PowerSI

Ansys SIwave

Keysight ADS

Ansys HFSS

Job description

Direct message the job poster from Datum Technologies Group

• Drive chip-package-system co-design by driving signal and power integrity requirements analysis and optimization
• Define power tree structure, netlists, etc for High Performance Computing based on 2.5D/3D package technology
• Run pre-layout and post-layout simulation flow with a focus on high-speed interface and PDN, create simulation models and develop simulation methodology for SIPI.
• Develop SIPI validation methodology and develop detailed engineering test plans
• Validate high speed interface and PDN impedance in lab to correlate simulation results and improve design flow
• Work closely with Architecture, ASIC, Mixed Signal, Package, and PCB Design teams to design and ensure package/system SI/PI performance meets expectation before Gerber out, also work closely with Design Validation teams to support SI/PI failure analysis
• Package/Board power delivery network AC+DC simulation for low-voltage/high-current supplies.
• Development of next generation memory interface considering Input/Output Physical Layer (IO PHY), SI/PI and physical design.

Preferred Qualifications:

• Bachelor or Master degree in Electrical Engineering, Physics, Mathematics, or related field (or equivalent experience)
• 5+ years of experience in SIPI simulation and validation areas
• Experience with high-speed interface protocols such as MIPI, PCIe, memory, HBM and USB.
• Experience using Cadecen Sigrity, PowerSI, Ansys SIwave, Keysight ADS, 3D layout and Ansys HFSS
• Experience with consumer hardware design, review and bring-up process, CAD tools, constraint manager etc.
• Solid understanding and experience in computational electromagnetics and transmission line theory.
• Drive chip-package-system co-design by driving signal and power integrity requirements analysis and optimization
• Define power tree structure, netlists, etc for High Performance Computing based on 2.5D/3D package technology
• Run pre-layout and post-layout simulation flow with a focus on high-speed interface and PDN, create simulation models and develop simulation methodology for SIPI.
• Develop SIPI validation methodology and develop detailed engineering test plans
• Validate high speed interface and PDN impedance in lab to correlate simulation results and improve design flow
• Work closely with Architecture, ASIC, Mixed Signal, Package, and PCB Design teams to design and ensure package/system SI/PI performance meets expectation before Gerber out, also work closely with Design Validation teams to support SI/PI failure analysis
• Package/Board power delivery network AC+DC simulation for low-voltage/high-current supplies.
• Development of next generation memory interface considering Input/Output Physical Layer (IO PHY), SI/PI and physical design.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Contract

Job function

• Industries

  Engineering Services and Semiconductor Manufacturing

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