ASIC Engineer, Senior Staff, Physical Design Verification

Juniper Networks, Inc; Sunnyvale (CA); On-site; USD 194,000 - 280,000; Full time

Job summary

An established industry player is seeking an ASIC Physical Verification Engineer to develop and support automated verification flows. This role requires expertise in physical verification, debugging complex issues, and collaborating with design teams. The ideal candidate will have extensive experience with industry-standard EDA tools and a proven track record in chip tapeouts. Join a dynamic environment where your contributions will directly impact innovative semiconductor designs, and enjoy a competitive compensation package that includes comprehensive benefits.

Benefits

Medical Benefits

401(k) Eligibility

Vacation

Sick Time

Parental Leave

Qualifications

• 7+ years in physical verification with a Bachelor's degree or 5+ years with a Master's.
• Proficient in EDA tools and debugging DRC/LVS issues.

Responsibilities

• Develop and support automated physical verification flows and scripts.
• Work with PD team to resolve DRC/LVS violations and sign off PV.

Skills

Physical Verification Flow

DRC/LVS/ESD/ERC/ANT/DFM Debugging

Linux Shell Scripting (Perl, TCL, Python)

Debugging Skills

Chip Tapeout Experience

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Tools

Mentor Calibre

Synopsys ICV

ICC/Innovus

Job description

Job Description for an ASIC Physical Verification Engineer

• Develop and support block and full chip automated physical verification flows and scripts


• Build Fullchip netlist & oasis database, execute metal and base-layer fill and integrate


• Perform block and full-chip physical verification, debug the issues and work with the physical design team to close design issues.


• Work with the PD team to clean up all DRC/LVS/ESD/ERC/ANT/DFM/latchup violations, Rule deck issues and sign off PV for tapeouts


• Work closely with semiconductor foundries and partners on installation, and maintenance of process design kits (PDKs) for ASIC physical design teams


• Understand and/or assist the PD team on pad ring, bump, RDL design, and working with the package and floorplan teams.

Minimum Qualifications

• Education:


• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 7+ years of experience in block or full-chip physical verification, or


• Master's degree in the above fields with 5+ years of related experience.


• Technical Expertise:


• In-depth understanding of physical verification flow and experience in analyzing and debugging DRC, ERC, LVS, DFM, antenna, ESD, latch-up, and rule deck issues.


• Proficiency with industry-standard physical verification EDA tools (e.g., Mentor Calibre, Synopsys ICV).


• Experience with PnR tools like ICC/Innovus for physical convergence.


• Preferable experience in Innovus/Fusion Compiler level DRC fixing.


• Proficiency in writing Linux shell scripts in Perl, TCL, and Python.


• Strong debugging skills.


• Real chip tapeout experience in 7nm and/or below with a successful signoff track record.


• Additional Skills:


• Experience in ASIC physical design and custom circuit design.


• Knowledge/Experience of ASIC timing signoff and EM/IR drop.


• Experience in IO, bump planning, and RDL routing strategy.


• Personal Attributes:


• Self-driven with a can-do attitude.


• Ability to work effectively in a dynamic group environment.

Minimum Salary: $194,400.00

Maximum Salary:$279,450.00

The pay range for this position is expected to be between $194,400.00 and $279,450.00/year; however, the base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. The total compensation package for this position also includes medical benefits, 401(k) eligibility, vacation, sick time, and parental leave. Additional details of participation in these benefit plans will be provided if an employee receives an offer of employment.

If hired, employee will be in an "at-will position" and the Company reserves the right to modify base salary (as well as any other payment or compensation program) at any time, including for reasons related to individual performance, Company or individual department/team performance, and market factors.

Juniper's pay range data is provided in accordance with local state pay transparency regulations. Juniper may post different minimum wage ranges for permanent residency petitions pursuant to US Department of Labor requirements.