Staff Engineer, ASIC Design, Front End

Samsung Semiconductor; San Jose (CA); On-site; USD 157,000 - 243,000; Full time

Job summary

An established industry player is seeking a Staff Engineer for ASIC Design, focusing on innovative HBM buffer die designs. This role involves collaborating with engineering teams to create cutting-edge solutions that meet market demands. With a competitive salary and a flexible work environment, this position offers a unique opportunity to contribute to next-generation semiconductor products. Ideal candidates will possess extensive experience in ASIC design, proficiency in Verilog, and a collaborative mindset. Join a forward-thinking organization that values innovation and inclusivity in the workplace.

Benefits

Flexible work arrangements

Wellness programs

Time off

Family support

Qualifications

• 10+ years experience in ASIC design or equivalent educational background.
• Proficiency in Verilog/System Verilog and waveform debugging.

Responsibilities

• Design architecture and RTL for customized HBM buffer die.
• Maximize bandwidth between HBM memory and logic die.

Skills

Verilog/System Verilog

Waveform debugging

Low-power design

Clock domain crossings

Firmware development

Scripting skills (Python, Perl, TCL, Shell)

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

PhD in Electrical Engineering

Job description

Join to apply for the Staff Engineer, ASIC Design, Front End role at Samsung Semiconductor

What You’ll Do

Product & Solution Planning (PSP) office is part of Samsung Semiconductor, Inc. (SSI). PSP’s mission is to create product and technology plans to exceed customer and market expectations and to build productization strategies for silicon products and solutions.

We are looking for a Staff ASIC Designer for customized HBM Buffer Die Design in San Jose, CA. The role involves creating and deploying HBM buffer die designs for next-generation products, collaborating with multiple engineering teams.

Responsibilities

• Architecture and RTL design for customized HBM buffer die
• Interface design to maximize bandwidth between HBM memory and logic die
• Low power design, including clock and power management, UPF file generation, and verification
• Scope third-party IP requirements and coordinate with vendors
• Perform LINT, CDC checks, static timing analysis, and generate constraints
• Understand DFT strategies, streaming scan fabric, IEEE protocols
• Experience with synthesis, DFT, functional verification, UVM verification

Qualifications

• Bachelor's in Electrical Engineering or related with 10+ years experience, or Master’s with 8+ years, or PhD with 5+ years
• Proficiency in Verilog/System Verilog
• Experience in waveform debugging, low-power design, clock domain crossings
• Design/verification of interface IPs and ARM Cortex systems
• Firmware development and scripting skills (Python, Perl, TCL, Shell)
• Inclusive, collaborative, innovative mindset

What We Offer

Competitive salary range: $157,000—$243,000 USD, with incentives, benefits, and a flexible, inclusive work environment. Our benefits include time off, family support, wellness programs, and flexible work arrangements.

Additional Details

Location: San Jose, CA (onsite per policy)
Seniority level: Mid-Senior level
Employment type: Full-time
Industry: Semiconductor Manufacturing