ASIC DFT Engineer

Cisco Systems, Inc.; California, San Jose (MO, CA); On-site; USD 90,000 - 150,000; Full time

Job summary

An established industry player seeks an ASIC Implementation Engineer to join their innovative Silicon One development team. This role focuses on Design-for-Test, requiring collaboration with Front-end RTL and physical design teams to ensure robust chip architecture. You'll lead the implementation of DFT features, driving quality processes throughout the design cycle and post-silicon validation phases. If you have a passion for cutting-edge technology and a strong background in ASIC design, this opportunity offers a dynamic environment where your contributions will shape the future of networking chips.

Qualifications

• 4+ years of experience in ASIC Design for Test Hardware Engineering.
• Strong understanding of DFT, test, and silicon engineering trends.

Responsibilities

• Implement Hardware Design-for-Test features for ATE and diagnostics.
• Collaborate with teams for full chip design integration and validation.

Skills

Jtag protocols

Scan architectures

BIST architectures

ATPG tools

System Verilog

Gate level simulation

Debugging with VCS

Scripting (Tcl, Python/Perl)

Education

Bachelor's Degree in Electrical Engineering

Master's Degree in Computer Engineering

Tools

TestMax

Tetramax

Tessent tool sets

PrimeTime

Job description

Who You'll Work With

You will be in the Silicon One development organization as an ASIC Implementation Engineer in San Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

What You'll Do

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.


• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.


• Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.


• The job requires the candidate to have the ability to craft and debug with minimal mentorship.

Who You Are

You are an ASIC Design for Test Hardware Engineer with 4+ years of related work experience with a broad mix of technologies including:

Minimum Requirements:

• A Bachelor's or Master's Degree, in Electrical or Computer Engineering required with at least 10 years of good experience of latest innovative trends in DFT, test and silicon engineering.


• Good experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.


• Good experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime


• Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design.


• Experience working with Gate level simulation, debugging with VCS and other simulators.


• Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687


• Strong verbal skills and ability to thrive in a multifaceted environment


• Scripting skills: Tcl, Python/Perl.

Preferred Skills:

• Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification


• DFT CAD development - Test Architecture, Methodology and Infrastructure


• Test Static Timing Analysis


• Post silicon validation using DFT patterns.