ASIC DFT Engineer

8613 Broadcom Corporation; San Jose (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) participation including company

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Job summary

Broadcom's ASIC Product Division in San Jose, CA is seeking an experienced ASIC DFT Engineer to join the development team. The role covers SoC DFT implementation, verification, and debug, including post-silicon bring up, test insertion, pattern generation, coverage improvements, and basic silicon debugging.

Collaboration with Physical Design and STA is essential. The ideal candidate has a strong DFT background and a track record in Verilog, ATPG/Scan, and memory BIST, with 10+ years in EE and

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or related field with 10+ years of experience.

Responsibilities

• Define DFT specifications for the ASIC including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration.
• Work closely with STA and DI Engineers to achieve design closure for test.
• Generate, verify and debug test vectors before tape release.
• Validate and debug test vectors on ATE during silicon bring up.
• Assist with silicon failure analysis, diagnostics and yield improvement.
• Interface with customers, physical design and test engineering/manufacturing teams globally.
• Collaborate with IP DFT engineers and other stakeholders.
• Debug customer returned parts on the ATE.
• Innovate newer DFT solutions to solve testability problems in 3nm & beyond.
• Automate DFT & test vector generation flows.

Skills

DFT background

ATPG/Scan

Verilog

Memory BIST

Test vector generation

Scripting: TCL/Perl/Python

ATE experience

Cross-functional collaboration

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

DFT Compiler

Mentor TestKompress

TetraMax

Fastscan

Simulation tools

Job description

ASIC DFT Engineer

Broadcom's ASIC Product Division is seeking candidates for a DFT Engineer position at our San Jose, California Development Center.

The successful candidate will participate in SoC DFT implementation, verification, and debug activities including post-silicon bring up. The candidate will support various phases of SoC DFT-related activities for Broadcom APD’s designs, including test insertion, pattern generation, coverage improvement, and basic silicon debug. The role involves collaborating with cross-functional teams, including Physical Design and STA engineers. Basic coding/scripting skills in TCL, Perl, Python, C++, or Verilog are expected.

Responsibilities

• Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
• Working closely with STA and DI Engineers design closure for test
• Generating, verifying & debugging test vectors before tape release
• Validating & debugging test vectors on ATE during the silicon bring up phase
• Assisting with silicon failure analysis, diagnostics & yield improvement efforts
• Interfacing with the customer, physical design and test engineering/manufacturing teams located globally
• Working closely with I/P DFT engineers & other stakeholders
• Debugging customer returned parts on the ATE
• Innovating newer DFT solutions to solve testability problems in 3nm & beyond
• Automating DFT & test vector generation flows

Skills / Experience

• Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
• Scan insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
• Logic BIST design and debug experience
• Well-versed in ATPG vector generation, simulation, debug. (TetraMax, Fastscan)
• Experience in Verilog coding, testbench generation & simulation
• Memory BIST insertion and verification experience (SRAM, CAM, eDRAM)
• The ability to work in a multi-disciplined, cross-department environment
• Solid knowledge in analog and digital circuit design, and device physics fundamentals
• Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
• Excellent problem solving, debug , root cause analysis and communication skills
• Experience working on ATE is a plus

Education & Experience

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with 10+ years of experience.

Compensation and Benefits

The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time

All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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