ASIC DFT Engineer

Broadcom, Inc.; Irvine (CA); On-site; USD 129,000 - 207,000; Full time

Benefits offered by this job

Annual bonus

Equity grants

401(k) matching

ESP P

Health, dental and vision plans

Paid holidays and vacation

Job summary

Broadcom's ASIC Product Division is seeking a DFT Engineer for ASIC/Chip level ATPG to lead DFT programs from specification through production release. You will collaborate with physical design, STA, and external customers to drive DFT architecture, test insertion, pattern generation, and yield improvement across 3nm and beyond.

The role involves extensive scripting automation (Python/TCL/C++), ATPG verification, and silicon bring-up with ATE testing to meet stringent test metrics.

Qualifications

• Strong DFT architecture and implementation background (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6)
• Experience with memory and logic BIST strategies, verification, and debug across embedded memories (SRAM, CAM, RF, ROM)
• Hands-on Verilog coding, testbench development, ATPG pattern generation, simulation, and timing constraints/Test-STA

Responsibilities

• Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC
• Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration
• Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns
• Collaborate with STA and design integration engineers for timing and design closure
• Generate, verify, and debug test vectors prior to tapeout release
• Validate and debug test vectors on ATE during silicon bring-up
• Assist with silicon failure analysis, diagnostics, and yield improvement efforts
• Interface with customers, physical design teams, and global test engineering/manufacturing teams
• Work with IP DFT engineers and cross-functional stakeholders
• Debug customer-returned parts (RMA) on ATE
• Develop DFT solutions for advanced process nodes (3nm+) and automate DFT/test vector flows

Skills

DFT architecture

ATPG pattern generation

Verilog coding

Testbench development

Debug and yield analysis

Python/TCL/C++ scripting

Cross-functional collaboration

Education

Bachelor's in Electrical/Electronic/Computer Engineering

12+ years of experience or Master’s with 10+ years

Tools

DFT Compiler

TestKompress

TetraMax

FastScan

Job description

USA-Colorado-Fort Collins-4380 Ziegler Road

USA-CA Irvine Alton Parkway Bldg 1

Full time

R027782

Job Description:

DFT Engineer for ASIC/Chip level ATPG

Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Fort Collins, Colorado, Development Center. The successful candidate will lead DFT programs from chip-level specification through implementation, verification, and product release to production.

The candidate will participate in all phases of SoC DFT activities for Broadcom APD (ASIC Products Division) designs, including DFT architecture, test insertion, verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement to meet product test metrics. Responsibilities also include collaborating with physical design and STA teams for DFT-mode timing closure and directly interfacing with external customers.

Responsibilities:

• Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC.

• Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration.

• Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns.

• Collaborate closely with STA and design integration engineers for timing and design closure.

• Generate, verify, and debug test vectors prior to tapeout release.

• Validate and debug test vectors on ATE during silicon bring-up.

• Assist with silicon failure analysis, diagnostics, and yield improvement efforts.

• Interface with customers, physical design teams, and global test engineering/manufacturing teams.

• Work closely with IP DFT engineers and cross-functional stakeholders.

• Debug customer-returned parts (RMA) on ATE.

• Proficiency in scripting and automation (such as Python, TCL, or C++), with an emphasis on applying AI-augmented development to streamline test flows.

• Develop innovative DFT solutions for advanced process nodes (3nm and beyond).

• Automate DFT and test vector generation flows.

Skills/Experience:

• Strong DFT architecture and implementation background (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6)

• Proficiency with EDA tools for scan insertion, compression, and ATPG (e.g., DFT Compiler, TestKompress, TetraMax, FastScan)

• Hands-on experience with memory and logic BIST strategies, verification, and debug across embedded memories (SRAM, CAM, RF, ROM)

• Experience with In-Field testing solutions a plus

• Extensive experience in Verilog coding, testbench development, ATPG pattern generation, simulation, and timing constraints/Test-STA

• Solid foundation in digital/analog circuit design, device physics, silicon manufacturing, synthesis, and transistor reliability

• Strong problem-solving, root-cause debug, statistical process control, and data analysis skills for silicon yield and quality improvement

• Effective cross-functional communication and project management skills to collaborate across physical design, test engineering, and operations

• Experience with ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN) is a plus

Education & Experience:

• Bachelors in Electrical/Electronic/Computer Engineering and 12+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 10+ years of relevant industry experience

Compensation and Benefits

The annual base salary range for this position is USD 129,400.00 To USD 207,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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