ASIC DFT Engineer

Broadcom, Inc.; Fort Collins (CO); On-site; USD 129,000 - 207,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) participation including company

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Company paid holidays

Paid sick leave and vacation time

Paid Family Leave and other leaves of

Job summary

Broadcom, Inc. is hiring a DFT Engineer for ASIC/Chip level ATPG at our Fort Collins Development Center. You will lead DFT programs from chip-level specification through implementation, verification, and product release to production.

The role covers SoC DFT activities, DFT architecture, test insertion, pattern generation, coverage improvement, post-silicon debug and yield improvements to meet test metrics. Proficiency in scripting and AI-augmented testing is valued.

Qualifications

• Experience with DFT architectures and chip-level implementation.
• Strong background in ATPG, pattern generation, and coverage improvement.
• Proficiency in Verilog, testbenches and timing constraints.

Responsibilities

• Lead DFT programs from spec to production release.
• Implement DFT architectures for ASICs and IP DFT integration.
• Gen and verify ATPG patterns; bring-up on ATE and silicon.

Skills

DFT architecture

ATPG

Verilog

Python

C++

AI-assisted testing

Education

Bachelors in Electrical/Electronic/Computer Engineering

Masters in Electrical/Electronic/Computer Engineering

Tools

DFT Compiler

TestKompress

TetraMax

FastScan

Job description

DFT Engineer for ASIC/Chip level ATPG

Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Fort Collins, Colorado, Development Center.

The successful candidate will lead DFT programs from chip-level specification through implementation, verification, and product release to production.

The candidate will participate in all phases of SoC DFT activities for Broadcom APD (ASIC Products Division) designs, including DFT architecture, test insertion, verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement to meet product test metrics.

Responsibilities

• Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC.
• Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration.
• Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns.
• Collaborate closely with STA and design integration engineers for timing and design closure.
• Generate, verify, and debug test vectors prior to tapeout release.
• Validate and debug test vectors on ATE during silicon bring-up.
• Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
• Interface with customers, physical design teams, and global test engineering/manufacturing teams.
• Work closely with IP DFT engineers and cross-functional stakeholders.
• Debug customer-returned parts (RMA) on ATE.
• Proficiency in scripting and automation (such as Python, TCL, or C++), with an emphasis on applying AI-augmented development to streamline test flows.
• Develop innovative DFT solutions for advanced process nodes (3nm and beyond).
• Automate DFT and test vector generation flows.

Skills/Experience

• Strong DFT architecture and implementation background (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6)
• Proficiency with EDA tools for scan insertion, compression, and ATPG (e.g., DFT Compiler, TestKompress, TetraMax, FastScan)
• Hands-on experience with memory and logic BIST strategies, verification, and debug across embedded memories (SRAM, CAM, eDRAM, ROM)
• Experience with In-Field testing solutions a plus
• Extensive experience in Verilog coding, testbench development, ATPG pattern generation, simulation, and timing constraints/Test-STA
• Solid foundation in digital/analog circuit design, device physics, silicon manufacturing, synthesis, and transistor reliability
• Strong problem-solving, root-cause debug, statistical process control, and data analysis skills for silicon yield and quality improvement
• Effective cross-functional communication and project management skills to collaborate across physical design, test engineering, and operations
• Experience with ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN) is a plus

Education & Experience

• Bachelors in Electrical/Electronic/Computer Engineering and 12+ years of relevant industry experience
• Masters Degree in Electrical/Electronic/Computer Engineering and 10+ years of relevant industry experience

Compensation and Benefits

The annual base salary range for this position is USD 129,400.00 To USD 207,000.00

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave and vacation time
• Paid Family Leave and other leaves of absence

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

About Us

We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Welcome! Thank you for your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video library and check out our Connected by Broadcom series. Follow us on Linked In Broadcom Inc.