ASIC Design Verification Engineer, DFT

Meta; Austin (TX); Sur place; USD 178 000 - 250 000; Plein temps

Avantages offerts par ce poste

Equity participation

Bonus program

Benefits package

Résumé du poste

Meta is hiring an ASIC Design Verification Engineer specializing in Design for Testability (DFT) within the Infrastructure Silicon team in Austin, TX. You will drive DFT verification closure across IP, sub-system, and SoC levels, ensuring scan, BIST, JTAG, and related structures are robust and verifiable.

You will collaborate with DFT Architects, Emulation, and Post-Silicon Validation teams to validate pre- and post-silicon results, develop scalable verification environments, and automate flows

Qualifications

• Requires 8+ years in ASIC design verification with SystemVerilog/UVM
• Deep experience with DFT verification: scan insertion, ATPG, BIST, JTAG
• Proficiency in scripting (Python/Tcl/Perl) for flow automation
• IP/SoC-level verification closure including test planning and coverage analysis
• Familiarity with formal verification for DFT control logic

Responsabilités

• Define DFT verification plans for scan, ATPG, BIST, JTAG across IP/sub-system/SoC
• Develop UVM- and C/C++-based testbenches to verify DFT logic
• Drive verification closure using functional, code, and DFT coverage metrics
• Review DFT insertion methods with architects and designers
• Debug root-cause DFT issues pre-silicon
• Develop and validate ATPG pattern generation flows
• Apply formal verification to DFT control logic and scan paths
• Collaborate with emulation and post-silicon teams for bring-up
• Build verification infrastructure and automated flows
• Contribute to ongoing DFT methodology improvements

Connaissances

UVM-based testbenches

SystemVerilog

DFT verification

Python scripting

Verification planning

Formation

Bachelor's degree in CS/CE or related field

Outils

EDA tools for DFT insertion/ATPG

Description du poste

Summary

Meta is hiring an ASIC Design Verification Engineer specializing in Design for Testability (DFT) within the Infrastructure Silicon organization. We are looking for experienced engineers to develop and verify DFT architectures for custom ASICs and System on Chip (SoC) designs powering Meta's data center infrastructure.In this role, you will drive DFT verification closure across IP, sub-system, and SoC levels, ensuring silicon manufacturability, testability, and quality for first-pass success. You will collaborate closely with Design, DFT Architecture, Emulation, and Post-Silicon Validation teams to develop robust verification environments that validate scan, BIST, JTAG, and other DFT structures using simulation, formal analysis, and emulation-based methodologies.

Required Skills

ASIC Design Verification Engineer, DFT Responsibilities:

1. Define and implement DFT verification plans covering scan insertion, ATPG, BIST, JTAG, and boundary scan structures at IP, sub-system, and SoC levels

2. Develop and maintain UVM-based and C/C++-based testbenches to verify DFT logic, including scan chains, memory BIST, and logic BIST controllers

3. Drive verification closure using defined metrics including functional coverage, code coverage, and DFT-specific structural coverage goals

4. Collaborate with DFT architects and design engineers to review DFT insertion methodologies and validate correctness of scan stitching and test access mechanisms

5. Debug and root-cause functional and structural failures in DFT logic, working closely with design and ATPG teams to resolve issues pre-silicon

6. Develop and validate ATPG test pattern generation flows, ensuring pattern quality and fault coverage targets are met

7. Apply formal verification techniques to prove correctness of DFT control logic, scan enable paths, and test mode isolation

8. Partner with emulation and post-silicon validation teams to enable DFT bring-up and correlate pre-silicon verification results with silicon test outcomes

9. Build and maintain verification infrastructure, scripts, and automation flows to improve DFT verification efficiency and reuse across projects

10. Contribute to continuous improvement of DFT verification methodologies, tools, and best practices across the infrastructure silicon team

Minimum Qualifications

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

2. 8+ years of hands-on experience in ASIC design verification using SystemVerilog and UVM-based methodologies

3. 8+ years of experience with DFT verification, including scan insertion, ATPG pattern validation, BIST verification, and JTAG/IEEE 1149.1 test access mechanisms

4. Experience with EDA tools for DFT insertion, ATPG, and simulation, along with scripting proficiency in Python, Tcl, Perl, or Shell for verification flow automation

5. Experience driving IP, sub-system, or SoC-level verification closure including test planning, testbench development, and coverage analysis

Preferred Qualifications

Preferred Qualifications:

1. Experience with formal verification techniques applied to DFT control logic, scan enable paths, or test mode isolation

2. Experience with DFT verification for AI/ML accelerator or networking ASIC designs in data center environments

3. Experience verifying high-speed interface DFT structures such as PCIe, HBM, DDR, or Ethernet SerDes

4. Experience with emulation platforms for DFT bring-up and pre-silicon to post-silicon correlation

Public Compensation

$178,000/year to $250,000/year + bonus + equity + benefits

Industry

Internet

Equal Opportunity

Meta is proud to be an Equal Employment Opportunity and Affidate action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].