ASIC Design Verification Engineer, DFT

Meta; Sunnyvale (CA); On-site; USD 146,000 - 209,000; Full time

Job summary

Meta is hiring an ASIC Design Verification Engineer specializing in DFT within the Infrastructure Silicon organization. We are looking for experienced engineers to develop and verify DFT architectures for custom ASICs and SoC designs powering Meta's data center infrastructure.

You will drive DFT verification closure across IP, sub-system, and SoC levels, ensuring silicon manufacturability, testability, and quality for first-pass success. Collaboration with multiple teams is essential.

Qualifications

• Bachelor's degree in CS/CE or equivalent practical experience.
• 6+ years of ASIC design verification using SystemVerilog and UVM-based methodologies.
• 6+ years of DFT verification including scan insertion, ATPG, BIST and JTAG/IEEE 1149.1.
• Experience with EDA tools for DFT insertion, ATPG, and simulation; scripting in Python, Tcl, Perl or Shell.
• Experience driving IP/sub-system/SoC verification closure including test planning, testbench development and coverage analysis.

Responsibilities

• Define and implement DFT verification plans covering scan insertion, ATPG, BIST, JTAG, and boundary scan structures at IP, sub-system, and SoC levels
• Develop and maintain UVM-based and C/C++-based testbenches to verify DFT logic, including scan chains, memory BIST, and logic BIST controllers
• Drive verification closure using functional coverage, code coverage, and DFT-specific structural coverage goals
• Collaborate with DFT architects and design engineers to review DFT insertion methodologies and validate scan stitching and test access
• Debug and root-cause functional and structural failures in DFT logic with design and ATPG teams pre-silicon
• Develop and validate ATPG test pattern generation flows, ensuring pattern quality and fault coverage targets
• Apply formal verification techniques to prove correctness of DFT control logic, scan enable paths, and test mode isolation
• Partner with emulation and post-silicon validation teams to enable DFT bring-up and correlate pre-silicon results with silicon tests
• Build and maintain verification infrastructure, scripts, and automation flows to improve DFT verification efficiency
• Contribute to continuous improvement of DFT verification methodologies, tools, and best practices

Skills

SystemVerilog

UVM

ATPG

BIST

JTAG

Python scripting

Education

Bachelor's degree in Computer Science, Computer Engineering, or equivalent

Job description

Meta is hiring an ASIC Design Verification Engineer specializing in Design for Testability (DFT) within the Infrastructure Silicon organization. We are looking for experienced engineers to develop and verify DFT architectures for custom ASICs and System on Chip (SoC) designs powering Meta's data center infrastructure.In this role, you will drive DFT verification closure across IP, sub-system, and SoC levels, ensuring silicon manufacturability, testability, and quality for first-pass success. You will collaborate closely with Design, DFT Architecture, Emulation, and Post-Silicon Validation teams to develop robust verification environments that validate scan, BIST, JTAG, and other DFT structures using simulation, formal analysis, and emulation-based methodologies.

ASIC Design Verification Engineer, DFT Responsibilities:

• Define and implement DFT verification plans covering scan insertion, ATPG, BIST, JTAG, and boundary scan structures at IP, sub-system, and SoC levels
• Develop and maintain UVM-based and C/C++-based testbenches to verify DFT logic, including scan chains, memory BIST, and logic BIST controllers
• Drive verification closure using defined metrics including functional coverage, code coverage, and DFT-specific structural coverage goals
• Collaborate with DFT architects and design engineers to review DFT insertion methodologies and validate correctness of scan stitching and test access mechanisms
• Debug and root-cause functional and structural failures in DFT logic, working closely with design and ATPG teams to resolve issues pre-silicon
• Develop and validate ATPG test pattern generation flows, ensuring pattern quality and fault coverage targets are met
• Apply formal verification techniques to prove correctness of DFT control logic, scan enable paths, and test mode isolation
• Partner with emulation and post-silicon validation teams to enable DFT bring-up and correlate pre-silicon verification results with silicon test outcomes
• Build and maintain verification infrastructure, scripts, and automation flows to improve DFT verification efficiency and reuse across projects
• Contribute to continuous improvement of DFT verification methodologies, tools, and best practices across the infrastructure silicon team

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 6+ years of hands-on experience in ASIC design verification using SystemVerilog and UVM-based methodologies
• 6+ years of experience with DFT verification, including scan insertion, ATPG pattern validation, BIST verification, and JTAG/IEEE 1149.1 test access mechanisms
• Experience with EDA tools for DFT insertion, ATPG, and simulation, along with scripting proficiency in Python, Tcl, Perl, or Shell for verification flow automation
• Experience driving IP, sub-system, or SoC-level verification closure including test planning, testbench development, and coverage analysis

Preferred Qualifications:

• Experience with formal verification techniques applied to DFT control logic, scan enable paths, or test mode isolation
• Experience verifying high-speed interface DFT structures such as PCIe, HBM, DDR, or Ethernet SerDes
• Experience with DFT verification for AI/ML accelerator or networking ASIC designs in data center environments
• Experience with emulation platforms for DFT bring-up and pre-silicon to post-silicon correlation

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Meta is proud to be an Equal Employment Opportunity and Aff… We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].

$146,000/year to $209,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.