ASIC Design Engineer - System-Level RTL & IP

NVIDIA Corporation; Austin (TX); Hybrid; USD 116,000 - 218,500; Full time

Benefits offered by this job

Generous benefits package

Equity options

Dynamic work environment

Job summary

NVIDIA Corporation is seeking an ASIC Design Engineer in Austin, Texas. The role involves defining and developing system-level methodologies and RTL to enhance GPU performance. As part of a dynamic team, you will collaborate with engineers and utilize your skills in RTL design and verification.

Ideal candidates require a BS in Electrical Engineering and 2+ years in industry, along with coding expertise in Perl/Python, Verilog, and SystemVerilog. Join us for a competitive salary and a vibrant workplace where innovation thrives.

Qualifications

• 2+ years of relevant industry experience.
• Good understanding of SOC architecture.
• Exposure to design and verification tools.

Responsibilities

• Define and develop system-level methodologies and RTL.
• Automate flows and methodologies for system-level IP.
• Run and debug RTL checks to ensure design quality.

Skills

Coding skills in Perl/Python

RTL design (Verilog)

Verification (SystemVerilog)

Design automation

Excellent debugging skills

Collaboration skills

Education

BS in Electrical Engineering or related field

MS or PhD (advanced degree)

Tools

dc_shell or equivalent synthesis tools

VCS or equivalent simulation tools

Debug tools (Debussy, GDB)

Job description

NVIDIA Corporation is seeking an ASIC Design Engineer in Austin, Texas. The role involves defining and developing system-level methodologies and RTL to enhance GPU performance. As part of a dynamic team, you will collaborate with engineers and utilize your skills in RTL design and verification.

Ideal candidates require a BS in Electrical Engineering and 2+ years in industry, along with coding expertise in Perl/Python, Verilog, and SystemVerilog. Join us for a competitive salary and a vibrant workplace where innovation thrives.