New Grad ASIC Design Engineer – RTL/SoC for GPUs (Equity)

NVIDIA Corporation; Santa Clara (CA); On-site; USD 100,000 - 189,750; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation seeks an ASIC Design Engineer for New College Grad 2026 in Santa Clara, CA. You will implement and verify high-performance RTL, focusing on area and power efficiency, and collaborate with cross-functional teams across pre- and post-silicon verification and back-end flow.

The role requires a Bachelors in ECE/CE/CS, with RTL/Verilog experience and knowledge of ASIC design flow. Strong problem-solving and teamwork are essential; equity and benefits are provided.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science.
• Experience with micro-architecture and RTL development (Verilog).
• Knowledge of ASIC design flow including RTL design, verification, synthesis and timing analysis.

Responsibilities

• Implement, document and deliver high performance, area and power efficient RTL to meet design targets.
• Analyze architectural trade-offs based on features, performance, and system limits.
• Collaborate with architects, designers, verification teams, and back-end teams to deliver tasks.

Skills

Verilog RTL design

C/C++

Python

Education

Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science

Job description

NVIDIA Corporation seeks an ASIC Design Engineer for New College Grad 2026 in Santa Clara, CA. You will implement and verify high-performance RTL, focusing on area and power efficiency, and collaborate with cross-functional teams across pre- and post-silicon verification and back-end flow.

The role requires a Bachelors in ECE/CE/CS, with RTL/Verilog experience and knowledge of ASIC design flow. Strong problem-solving and teamwork are essential; equity and benefits are provided.