Senior ASIC Design Engineer

NVIDIA; Santa Clara (CA); On-site; USD 168,000 - 264,500; Full time

Benefits offered by this job

Equity

Comprehensive benefits

Job summary

NVIDIA is looking for a Senior ASIC Design Engineer based in Santa Clara, California. You will be a key member of the GPU Design team, implementing high-performance, area-efficient RTL for leading SoCs and GPUs.

The ideal candidate has a Bachelor's degree in Electrical Engineering or similar, with 8+ years of experience in micro-architecture and RTL development. Strong C/C++ and Verilog skills are a plus. This position offers a competitive salary, equity, and benefits.

Qualifications

• 8+ years of meaningful work experience.
• Great understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
• Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic.

Responsibilities

• Implement, document and deliver high performance, area and power efficient RTL.
• Analyze architectural trade‑offs based on features and performance requirements.
• Collaborate with architects, designers, and verification teams.

Skills

Micro-architecture and RTL development (Verilog)

Strong C/C++, Python or Perl skills

Debugging and analytical skills

Education

Bachelor's Degree in Electrical Engineering, Computer Engineering or Computer Science

Job description

We are now looking for a Senior ASIC Design Engineer.

NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoCs and GPUs.

What you'll be doing:

• As a key member of the GPU Design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
• Analyze architectural trade‑offs based on features, performance requirements and system limitations.
• Craft micro‑architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design.
• Collaborate and coordinate with architects, other designers, pre‑ and post‑silicon verification teams, synthesis, timing and back‑end teams to accomplish your tasks.
• Work on a broad list of IPs such as GPU's work scheduler, time distribution system, interrupt controllers, and DMA engines.
• Architect features to help silicon debug and support post‑silicon validation activities.

What we need to see:

• Bachelors Degree or equivalent experience in Electrical Engineering, Computer Engineering or Computer Science.
• 8+ years of meaningful work experience.
• Experience in micro‑architecture and RTL development (Verilog), focused on arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches.
• Great understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
• Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic is required.
• Strong interpersonal skills and an excellent teammate.

Ways to stand out from the crowd:

• Strong C/C++, Python or Perl skills.
• Good debugging and analytical skills.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

You will also be eligible for equity and benefits.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.