ASIC Design Engineer — Equity & RTL DevOps

NVIDIA Corporation; Austin (TX); Hybrid; USD 116,000 - 219,000; Full time

Job summary

NVIDIA Corporation in Austin, TX is seeking an ASIC Design Engineer to join a world-class team focused on hardware design and methodology for GPUs and AI accelerators. You will help amplify human creativity and intelligence through robust design and verification workflows.

The role emphasizes developing in-house tools, owning verification blocks, and enabling automated RTL generation and seamless integration with IP development environments. A hybrid work model is supported.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering (or equivalent).
• 3+ years of proven experience preferred.
• Solid understanding of fundamental digital design concepts with hands-on experience in Verilog.
• Proficiency in scripting using modern Python and/or Perl.

Responsibilities

• Develop and deploy in-house tools to support engineering business units.
• Take ownership of tools that verify common design blocks used in all NVIDIA products.
• Act as a DevOps engineer for automated RTL generation by developing new features and maintaining efficient operations for existing users.
• Build new workflows and methodologies to ensure smooth integration into various IP development environments.

Skills

Verilog

Python

Perl

Unix shells

Makefiles

Collaboration

Education

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering (or equivalent experience)

Tools

Makefiles

Job description

NVIDIA Corporation in Austin, TX is seeking an ASIC Design Engineer to join a world-class team focused on hardware design and methodology for GPUs and AI accelerators. You will help amplify human creativity and intelligence through robust design and verification workflows.

The role emphasizes developing in-house tools, owning verification blocks, and enabling automated RTL generation and seamless integration with IP development environments. A hybrid work model is supported.