ASIC Design Engineer - GPU/SoC (New Grad) | Equity

NVIDIA; Santa Clara (CA); On-site; USD 100,000 - 167,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in Santa Clara, CA seeks an ASIC Design Engineer - New College Graduate to implement high-performance RTL for leading SoCs and GPUs. You will collaborate with design, verification, and backend teams on IPs like schedulers, interrupt controllers, and DMA engines, contributing to post-silicon validation.

Excellent collaboration and strong fundamentals in RTL design, micro-architecture, and modern programming are essential as you grow in a dynamic AI/graphics hardware environment with equity

Qualifications

• Pursuing or recently completed a BS or MS in Electrical Engineering, Computer Engineering or Computer Science or related field or equivalent experience.
• Knowledge of micro-architecture and RTL development (Verilog).
• Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.

Responsibilities

• As a key member of the GPU Design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
• Analyze architectural trade-offs based on features, performance requirements and system limitations.
• Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design.
• Collaborate with architects, other designers, verification teams, synthesis, timing and back-end teams.
• Work on IPs such as GPU work scheduler, time distribution system, interrupt controllers, and DMA engines.
• Architect features to help silicon debug and support post-silicon validation activities.

Skills

RTL development (Verilog)

Micro-architecture knowledge

C/C++

Python

Education

BS/MS in Electrical Engineering / Computer Engineering / Computer Science

Tools

Verilog

Job description

NVIDIA in Santa Clara, CA seeks an ASIC Design Engineer - New College Graduate to implement high-performance RTL for leading SoCs and GPUs. You will collaborate with design, verification, and backend teams on IPs like schedulers, interrupt controllers, and DMA engines, contributing to post-silicon validation.

Excellent collaboration and strong fundamentals in RTL design, micro-architecture, and modern programming are essential as you grow in a dynamic AI/graphics hardware environment with equity