ASIC Engineer Intern

NWU; Sunnyvale (CA); On-site; USD 48,000 - 63,000; Full time

Benefits offered by this job

Comprehensive benefits supporting well

Professional development programs

Inclusive work environment with flex

Job summary

NWU is offering an internship for students in Electrical Engineering, Computer Engineering, or Computer Science. You will focus on one ASIC area—Design, Verification, or Tools & Methodologies—and collaborate with senior engineers to learn processes.

The role emphasizes hands-on work with SystemVerilog, UVM, and scripting in Python or C++. You will participate in team meetings, learn project methodologies, and contribute to improving development flows.

Qualifications

• Pursuing a bachelor’s or master’s degree in a technical field.
• Coursework in digital logic, computer architecture, or VLSI design is desirable.
• Exposure to SystemVerilog, UVM, and basic Python/C++ is expected.

Responsibilities

• Focus on one ASIC area: Design, Verification, or Tools & Methodologies.
• Collaborate with senior engineers to troubleshoot issues and propose solutions.
• Participate in team meetings and learn project methodologies.
• Engage in learning new technologies and best practices in your focus area.
• Complete assigned tasks efficiently and incorporate feedback.
• Support ongoing design/verification/test activities as needed.

Skills

Analytical thinking

Communication skills

Time management

Team collaboration

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science

Coursework in Digital Logic Design, Computer Architecture, or VLSI Design

Tools

SystemVerilog

UVM

Python

C++

Job description

Your Role

Here’s what you will be doing:

• Focus on one of three ASIC areas: Design, Verification, or Tools & Methodologies, working closely with senior engineers.
• ASIC Design: Participate in architecture investigations, create specifications, assist in RTL design with SystemVerilog, support synthesis, linting, and design reviews.
• ASIC Verification: Develop and maintain testbenches using SystemVerilog and UVM, write test plans and assertions, create coverage models, debug simulations, contribute to regression setup, and participate in emulation activities.
• Tools & Methodologies: Automate ASIC development processes, improve flows, evaluate EDA tools, develop productivity utilities, work with physical design tools, and support Design-for-Test methodology.
• Collaborate with team members to troubleshoot technical issues and propose solutions.
• Participate in team meetings, learn project methodologies, share progress during reviews.
• Engage in learning new technologies and best practices relevant to your focus area.
• Complete assigned tasks efficiently and incorporate feedback.

About You

The company is looking for:

• Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.
• Coursework in Digital Logic Design, Computer Architecture, or VLSI Design is highly desirable.
• Familiarity with ASIC concepts through academic projects or internships is a plus.
• Exposure to SystemVerilog, UVM, and basic knowledge of Python, C++, or similar languages.
• Understanding of ASIC design flow, verification methodologies, and EDA tools for physical design.
• Strong analytical and problem-solving skills.
• Excellent communication and interpersonal skills.
• Ability to manage time and meet deadlines.
• Passion for high-tech and continuous learning.
• Knowledge of networking protocols, machine learning, or advanced computer architecture is a plus.

Compensation & Benefits

• Hourly salary range for Bachelor’s students in California: USD 35.00 - 41.00.
• Hourly salary range for Master’s students in California: USD 40.00 - 46.00.
• Variable incentives may also be offered.
• Comprehensive benefits supporting physical, financial, and emotional wellbeing.
• Programs for personal and professional development to support career goals.
• Inclusive work environment valuing diverse backgrounds and flexible work arrangements.