Validation Engineer

TechDoQuest; San Jose (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

TechDoQuest in California is seeking an experienced ASIC verification engineer to verify complex blocks of SoCs as part of a joint CPU/GPU development effort. You will design and execute test plans using directed and constrained-random tests, and document verification procedures to ensure functional correctness.

The role requires 8–10 years of proven verification experience on large ASIC projects or equivalent software/firmware experience in hardware development, with a strong background in

Qualifications

• 8–10 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting.
• Strong background in C/C++ development in a Linux Environment.
• Proficient in Object Oriented programming, STL, computer architecture and data structures.
• Experience in Verilog/SystemVerilog/SystemC, preferred; DPI/PLI experience preferred.
• Strong debugging skills and experience with debug tools such as Gdb, Valgrind.
• Excellent written and communication skills; Prefer SoC verification experience and UVM (System Verilog).

Responsibilities

• Participate in the functional verification of ASIC blocks and IP cores.
• Documentation and execution of test plan(s) with directed and constrained-random tests during simulation.
• Adopt evolving verification methodologies for complex SoCs within aggressive schedules.
• Work within the existing verification infrastructure on active projects and collaborate with design/verification teams.

Skills

C/C++ development

Debugging skills

Object oriented programming

Computer architecture

Data structures

Communication skills

Analytical skills

Tools

GDB

Valgrind

Perl

Makefiles

Verilog/SystemVerilog/SystemC

DPI/PLI

Job description

Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for

a combined CPU/GPU development effort.

Be part of a team of design and verification engineers, working closely with other team

members to understand and verify the functionality of a given design element within the

context of the block, chip and overall system.

Be responsible for carefully documenting and executing test plan(s) consisting of directed

and constrained-random tests to be run during simulation.

Be expected to adopt the evolving verification methodologies used in the industry to

functionally verify increasingly more complex SoC designs within aggressive, market-

driven schedules, and work within the existing verification infrastructure on currently

active projects. Be familiar with hardware modeling and/or assertion-based verification

methods.

EXPERIENCE AND EDUCATION:

8-10 years of proven verification experience on large ASIC development projects or

software/firmware experience in a hardware development setting;

Strong background in C/C++ development in a Linux Environment;

Strong debug skills and experience with debug tools such as Gdb, Valgrind;

Proficient in Object Oriented programming, STL, computer architecture and data

structures;

Knowledge of Perl and Makefiles;

Experience in Verilog/SystemVerilog/SystemC, preferred;

Experience in C/Verilog environment using DPI/PLI, preferred;

Strong analytical skills and attention to detail; Excellent written and communication skills

Prefer SoC verification experience and UVM. (System Verilog)