Application Engineer Architect (STA SignOff)

Cadence; Salem (OR); Sur place; USD 154 000 - 286 000; Plein temps

Avantages offerts par ce poste

Paid vacation

Paid holidays

401(k) with employer match

Employee stock purchase plan

Medical, dental and vision plan

Résumé du poste

Cadence in Oregon seeks a Senior IC Design Signoff Lead with 15+ years of experience to steer timing signoff across advanced nodes. You will lead technical engagements with customers, collaborate with R&D and Product Engineering, and drive innovative methodologies for Power/Timing closure and STA.

You will represent Cadence at industry events and publish technical papers, while mentoring teams and influencing stakeholders at executive levels.

Qualifications

• 15+ years of experience in IC design implementation and signoff.
• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• Deep expertise in digital design fundamentals, STA & ECOs (3nm and below), and EDA tool ecosystems.
• Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions.

Responsabilités

• Lead technical engagements with customers and partners to drive adoption of Cadence signoff portfolio.
• Partner with R&D and Product Engineering to influence tool enhancements based on customer requirements.
• Drive benchmarks, flow optimizations, and deployment of timing signoff methods across nodes.
• Represent Cadence at industry forums and deliver technical papers and presentations.

Connaissances

Tcl scripting

Python scripting

Perl scripting

Leadership

Communication

Negotiation

Formation

BS/MS in Electrical Engineering or Computer Engineering

Outils

Tempus

Certus

QRC

Description du poste

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Key Responsibilities

• Technical Expertise: Lead technical engagements with customers and partners to drive & adoption of Cadence signoff portfolio. Work closely with design teams to meet customer success metrics, guide adoption of Cadence's timing signoff & closure and AgenticAI features across advanced nodes (5nm and below).
• Cross-Functional Collaboration: Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements.
• Innovation & Enablement: Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for timing sigoff & closure, STA, IR Drop, and power/timing closure.
• Thought Leadership: Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.

Qualifications

• 15+ years of experience in IC design implementation and signoff, with demonstrated success in managing large-scale technical programs.
• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• Deep expertise in digital design fundamentals, advanced node STA & ECOs (3nm and below), and EDA tool ecosystems.
• Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions
• Proven track record of leading technical teams and driving customer success at executive levels.
• Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure.
• Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders.
• Prior experience with Cadence tools (Tempus, Certus, QRC) and competitive solutions highly desirable.

The annual salary range for Washington is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.

• Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.